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ST72325AR7-Auto Datasheet(PDF) 42 Page - STMicroelectronics

No. de pieza ST72325AR7-Auto
Descripción Electrónicos  SCI asynchronous serial interface
PDF  243 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72325AR7-Auto Datasheet(HTML) 42 Page - STMicroelectronics

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Obsolete
Product(s)
- Obsolete
Product(s)
Supply, reset and clock management
ST72325xxx-Auto
42/243
Doc ID 13770 Rev 3
6
Supply, reset and clock management
6.1
Introduction
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components. An overview is shown in Figure 10.
For more details, refer to the dedicated parametric section.
6.2
Main features
Optional PLL for multiplying the frequency by 2 (not to be used with internal RC
oscillator)
Reset Sequence Manager (RSM)
Multi-oscillator Clock Management (MO)
5 crystal/ceramic resonator oscillators
1 internal RC oscillator
System Integrity Management (SI)
Main supply low voltage detection (LVD)
Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main
supply
Clock security system (CSS) with clock filter and backup safe oscillator (enabled
by option byte)
Figure 10.
Clock, reset and supply block diagram
LOW VOLTAGE
DETECTOR
(LVD)
fOSC2
AUXILIARY VOLTAGE
DETECTOR
(AVD)
MULTI-
OSCILLATOR
(MO)
OSC1
RESET
VSS
EVD
VDD
RESET SEQUENCE
MANAGER
(RSM)
CLOCK
FILTER
SAFE
OSC
CLOCKSECURITYSYSTEM
(CSS)
OSC2
MAIN CLOCK
CSS Interrupt Request
AVD Interrupt Request
CONTROLLER
PLL
SYSTEM INTEGRITY MANAGEMENT
WATCHDOG
SICSR
TIMER (WDG)
WITH REALTIME
CLOCK (MCC/RTC)
AVD AVD AVD LVD
RF
CSS
IE
IE
CSS
D
WDG
RF
0
1
fOSC
fOSC2
(option)
0
S
F
fCPU



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