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ST72325AR7-Auto Datasheet(PDF) 25 Page - STMicroelectronics |
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ST72325AR7-Auto Datasheet(HTML) 25 Page - STMicroelectronics |
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25 / 243 page ![]() Obsolete Product(s) - Obsolete Product(s) ST72325xxx-Auto Package pinout and pin description Doc ID 13770 Rev 3 25/243 42 30 PC7/SS/AIN15 I/O CT X XX X X Port C7 SPI Slave Select (active low) ADC analog Input 15 43 -(1) PA0 I/O CT X ei0 X X Port A0 44 -(1) PA1 I/O CT X ei0 X X Port A1 45 -(1) PA2 I/O CT X ei0 X X Port A2 46 31 PA3 (HS) I/O CT HS X ei0 X X Port A3 47 32 VDD_1 (2) S Digital Main Supply Voltage 48 33 VSS_1 (2) S Digital Ground Voltage 49 34 PA4 (HS) I/O CT HS X XX X Port A4 50 35 PA5 (HS) I/O CT HS X XX X Port A5 51 36 PA6 (HS)/SDAI I/O CT HS X T Port A6 I2C Data 52 37 PA7 (HS)/SCLI I/O CT HS X T Port A7 I2C Clock 53 38 VPP/ ICCSEL I Must be tied low. In Flash programming mode, this pin acts as the programming voltage input VPP. See Section 19.9.2 for more details. 54 39 RESET I/O CT Top priority non maskable interrupt. 55 - EVD I A External voltage detector 56 - TLI I CT X Top level interrupt input pin 57 40 VSS_2 (2) S Digital Ground Voltage 58 41 OSC2(3) I/O Resonator oscillator inverter output 59 42 OSC1(3) I External clock input or Resonator oscillator inverter input 60 43 VDD_2 (2) S Digital Main Supply Voltage 61 44 PE0/TDO I/O CT X X X X Port E0 SCI Transmit Data Out 62 1 PE1/RDI I/O CT X X X X Port E1 SCI Receive Data In 63 -(1) PE2 I/O CT X XX(4) X(4) Port E2 64 -(1) PE3 I/O CT X XX X Port E3 1. On the chip, each I/O port may have up to eight pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption. 2. It is mandatory to connect all available VDD and VAREF pins to the supply voltage and all VSS and VSSA pins to ground. 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1: Description and Section 19.5: Clock and timing characteristicsfor more details. 4. Pull-up always activated on PE2 (see Section 22.1.8: Pull-up always active on PE2). Table 3. Device pin descriptions (LQFP64 and LQFP44) (continued) Pin Level Port Main function (after reset) Alternate function No. Name Input Output |
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