ST72325AR7-Auto datasheet(52/243 Pages) STMICROELECTRONICS

52 / 243 page

Obsolete

Product(s)

- Obsolete

Product(s)

Supply, reset and clock management

ST72325xxx-Auto

52/243

Doc ID 13770 Rev 3

6.6.6

System Integrity (SI) Control/Status register (SICSR)

SICSR

Reset value:

000x 000x (00h)

543

AVDS

AVDIE

AVDF

LVDRF

Reserved

WDGRF

Table 14.

SICSR description

Bit

Name

Function

7AVDS

Voltage Detection selection

This bit is set and cleared by software. Voltage Detection is available only if the

LVD is enabled by option byte.

0: Voltage detection on VDD supply

1: Voltage detection on EVD pin

AVDIE

Voltage Detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated

when the AVDF flag changes (toggles). The pending interrupt information is

automatically cleared when software enters the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

5AVDF

Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an

interrupt request is generated when the AVDF bit changes value. Refer to

Figure 16 and to Monitoring the VDD main supply on page 48 for additional

details.

0: VDD or VEVD over VIT+(AVD) threshold

1: VDD or VEVD under VIT-(AVD) threshold

LVDRF

LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by

hardware (LVD reset) and cleared by software (writing zero). See Table 15: Reset

source flags for more details. When the LVD is disabled by OPTION BYTE, the

LVDRF bit value is undefined.

Reserved, must be kept cleared.

CSSIE

Clock security system interrupt enable

This bit enables the interrupt when a disturbance is detected by the Clock Security

System (CSSD bit set). It is set and cleared by software.

0: Clock security system interrupt disabled

1: Clock security system interrupt enabled

When the CSS is disabled by OPTION BYTE, the CSSIE bit has no effect.

CSSD

Clock security system detection

This bit indicates that the safe oscillator of the Clock Security System block has

been selected by hardware due to a disturbance on the main clock signal (fOSC). It

is set by hardware and cleared by reading the SICSR register when the original

oscillator recovers.

0: Safe oscillator is not active

1: Safe oscillator has been activated

When the CSS is disabled by OPTION BYTE, the CSSD bit value is forced to 0.

ST72325AR7-Auto Datasheet(PDF) 52 Page - STMicroelectronics

ST72325AR7-Auto Datasheet(HTML) 52 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL