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ST72325AR7-Auto Datasheet(PDF) 19 Page - STMicroelectronics |
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ST72325AR7-Auto Datasheet(HTML) 19 Page - STMicroelectronics |
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19 / 243 page ![]() Obsolete Product(s) - Obsolete Product(s) ST72325xxx-Auto Description Doc ID 13770 Rev 3 19/243 Figure 1. Device block diagram 1. On certain devices only (see Device summary) 8-BIT CORE ALU OSC1 VPP CONTROL PROGRAM 16 - 60 Kbytes(1) VDD RESET PORT F PF7:0 TIMER A BEEP RAM 512 - 2048 bytes(1) PORT C VAREF VSSA PB7:0 PORT E PE7:0 (2 bits on J/K devices) SCI TIMER B PA7:0 (5 bits on J devices) PORT D PD7:0 SPI PC7:0 (8 bits) VSS WATCHDOG OSC LVD OSC2 MEMORY MCC/RTC/BEEP (4 bits on K devices) (5 bits on J devices) (3 bits on K devices) (6 bits on J devices) (2 bits on K devices) (6 bits on J devices) (5 bits on K devices) PORT A PORT B PWM ART I2C EVD AVD (8 bits on R/AR devices) (8 bits on R/AR devices) (8 bits on R/AR devices) (8 bits on R/AR devices) (8 bits on R/AR devices) TLI DEBUG MODULE 10-BIT ADC |
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