ST72325AR7-Auto datasheet(93/243 Pages) STMICROELECTRONICS

93 / 243 page

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ST72325xxx-Auto

PWM auto-reload timer (ART)

Doc ID 13770 Rev 3

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Figure 38.

Output compare control

12.2.5

Independent PWM signal generation

This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx

output pins with minimum core processing overhead. This function is stopped during Halt

mode.

Each PWMx output signal can be selected independently using the corresponding OEx bit

in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is

configured as output push-pull alternate function.

The PWM signals all have the same frequency which is controlled by the counter period and

the ARTARR register value.

fPWM = fCOUNTER / (256 - ARTARR)

When a counter overflow occurs, the PWMx pin level is changed depending on the

corresponding OPx (output polarity) bit in the PWMCR register. When the counter reaches

the value contained in one of the output compare register (OCRx) the corresponding PWMx

pin level is restored.

It should be noted that the reload values will also affect the value and the resolution of the

duty cycle of the PWM output signal. To obtain a signal on a PWMx pin, the contents of the

OCRx register must be greater than the contents of the ARTARR register.

The maximum available resolution for the PWMx duty cycle is:

Resolution = 1 / (256 - ARTARR)

Note:

To get the maximum resolution (1/256), the ARTARR register must be 0. With this maximum

resolution, 0% and 100% can be obtained by changing the polarity.

COUNTER

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

ARTARR = FDh

fCOUNTER

OCRx

PWMDCRx

FDh

FEh

FDh

FEh

FFh

PWMx

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