TNETV1644ZDU6 datasheet(140/306 Pages) TI1

140 / 306 page

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Table 3-49. EMIFA/VPSS Sub-Block 0 Configuration Choice G(1)

MAJOR

MINOR

PINMUX SELECTION FIELDS

RESULTING PERIPHERALS/PINS

CONFIG

PCIEN

AEM

AEAW

OTHERS

PCI

EMIFA

VPFE

# GPIO PINS

OPTION

8-bit EMIFA

(NAND)

Cfg Summary

PCI

No CCDC

13 GP pins

Pinout mode

0 = GP[54,

CCDCSEL = 0

43:36]

HVDSEL = 0

0 = GP[53:52]

CWENSEL = 0

0 = GP[35]

101

000

CFLDSEL = 0

0 = GP[34]

0 = PREQ,

CI10SEL = 0

PINTA

0 = AD31,

CI32SEL = 0

PRST

0 = AD29,

CI54SEL = 0

PGNT

0 = AD25,

CI76SEL = 0

AD27

8-bit EMIFA

(NAND)

Cfg Summary

PCI

8-bit CCDC

0-to-4 GP pins

Pinout mode

1 = PCLK,

CCDCSEL = 1

YI[7:0]

HVDSEL = 0,1

1 = VD, HD

0 = GP[53:52]

CWENSEL = 0,1

1 = C_WE

0 = GP[35]

101

000

CFLDSEL = 0,1

1 = C_FIELD

0 = GP[34]

0 = PREQ,

CI10SEL = 0

PINTA

0 = AD31,

CI31SEL = 0

PRST

0 = AD29,

CI54SEL = 0

PGNT

0 = AD25,

CI76SEL = 0

AD27

(1)

Italics indicate mandatory settings for a given Minor Configuration option.

As shown in Table 3-43 through Table 3-49, the configuration choices of the EMIFA/VPSS Sub-Block 0

are determined by the following PINMUX register fields:

• PINMUX1 register field PCIEN

• PINMUX0 register fields AEM, AEAW, CCDCSEL, HVDSEL, CWENSEL, CFLDSEL, CI10SEL,

CI32SEL, CI54SEL, and CI76SEL.

140

Device Configurations

Submit Documentation Feedback

TNETV1644ZDU6 Datasheet(PDF) 140 Page - Texas Instruments

TNETV1644ZDU6 Datasheet(HTML) 140 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL