TNETV1644ZDU6 datasheet(143/306 Pages) TI1

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TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

Table 3-50. EMIFA/VPSS Sub-Block 1 Configuration Choices A and F(1)

MAJOR

MINOR

PINMUX SELECTION FIELDS

RESULTING PERIPHERALS/PINS

CONFIG

AEM

OTHERS

EMIFA

VPBE

GPIO

OPTION

Cfg Summary

No EMIFA

No VENC

29 GP pins

VENCSEL = 0

0 = GP[31, 29:14]

RGBSEL = 0

0 = GP[12:5]

A1, F1

000

CS3SEL = 0

0 = GP[13]

CS4SEL = 0

0 = GP[32]

CS5SEL = 0

0 = GP[33]

VPBECKEN = 0

0 = GP[30]

Cfg Summary

No EMIFA

8-bit VENC

8 to 29 GP pins

1 = VCLK,

VENCSEL = 1

1 = GP[21:14]

YOUT[7:0]

0 = GP[12:5]

0 = none

RGBSEL = 0,1

1 = GP[12],

1 = LCD_FIELD

A2, F2

000

GP[10:5]

CS3SEL = 0,2

2 = LCD_OE

0 = GP[13]

CS4SEL = 0,2

2 = VSYNC

0 = GP[32]

A, F

CS5SEL = 0,2

2 = HSYNC

0 = GP[33]

VPBECKEN = 0,1

1 = VPBECLK

0 = GP[30]

Cfg Summary

No EMIFA

16-to-24-bit VENC

0 to 12 GP pins

2 = VCLK,

VENCSEL = 2

YOUT[7:0],

COUT[7:0]

0 = none

0 = GP[12:5]

1 = LCD_FIELD

1 = GP[12],

2 = R2, B2

GP[10:5]

RGBSEL = 0,1,2,3,4

3 = R2, B2,

2 = GP[12:7]

A3, F3

000

LCD_FIELD

3 = GP[12],

4 = G0, B0, R0, G1,

GP[10:7]

B1, R1, R2, B2

4 = No GP

CS3SEL = 0,2

2 = LCD_OE

0 = GP[13]

CS4SEL = 0,2

2 = VSYNC

0 = GP[32]

CS5SEL = 0,2

2 = HSYNC

0 = GP[33]

VPBECKEN = 0,1

1 = VPBECLK

0 = GP[30]

(1)

Italics indicate mandatory settings for a given Minor Configuration option.

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TNETV1644ZDU6 Datasheet(PDF) 143 Page - Texas Instruments

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