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TNETV1644ZDU6 Datasheet(PDF) 81 Page - Texas Instruments

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No. de pieza TNETV1644ZDU6
Descripción Electrónicos  Digital Media Processor
PDF  306 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TNETV1644ZDU6 Datasheet(HTML) 81 Page - Texas Instruments

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TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 3-5. Non-Fastboot Modes (FASTBOOT = 0)
DEVICE BOOT AND
PLLC1 CLOCK SETTING AT BOOT
CONFIGURATION PINS
DM6437 DMP
DSPBOOTADDR
BOOT DESCRIPTION(1)
DEVICE
(Master/Slave)
(DEFAULT)(1)
PLL
CLKDIV1 DOMAIN
BOOTMODE[3:0]
PCIEN
FREQUENCY
MODE(2)
(SYSCLK1 DIVIDER)
(SYSCLK1)
0000
0 or 1
No Boot (Emulation Boot)
Master
Bypass
/1
CLKIN
0x0010 0000
0001
0 or 1
Reserved
–
–
–
–
–
0
HPI Boot
Slave
Bypass
/1
CLKIN
0x0010 0000
0010
1
Reserved
–
–
–
–
–
0011
0 or 1
Reserved
–
–
–
–
–
EMIFA ROM Direct Boot
0100
0 or 1
Master
Bypass
/1
CLKIN
0x4200 000
[PLL Bypass Mode]
I2C Boot
0101
0 or 1
Master
Bypass
/1
CLKIN
0x0010 0000
[STANDARD MODE](3)
16-bit SPI Boot
0110
0 or 1
Master
Bypass
/1
CLKIN
0x0010 0000
[McBSP0]
0111
0 or 1
NAND Flash Boot
Master
Bypass
/1
CLKIN
0x0010 0000
UART Boot without
1000
0 or 1
Hardware Flow Control
Master
Bypass
/1
CLKIN
0x0010 0000
[UART0]
1001
0 or 1
Reserved
–
–
–
–
–
1010
0 or 1
VLYNQ Boot
Slave
Bypass
/1
CLKIN
0x0010 0000
1011
0 or 1
Reserved
–
–
–
–
–
1100
0 or 1
Reserved
–
–
–
–
–
1101
0 or 1
Reserved
–
–
–
–
–
UART Boot with
1110
0 or 1
Hardware Flow Control
Master
Bypass
/1
CLKIN
0x0010 0000
[UART0]
24-bit SPI Boot
1111
0 or 1
Master
Bypass
/1
CLKIN
0x0010 0000
(McBSP0 + GP[97])
(1)
For all boot modes that default to DSPBOOTADDR = 0x0010 0000 (i.e., all boot modes except the EMIFA ROM Direct Boot,
BOOTMODE[3:0] = 0100, FASTBOOT = 0), the bootloader code disables all C64x+ cache (L2, L1P, and L1D) so that upon exit from the
bootloader code, all C64x+ memories are configured as all RAM. If cache use is required, the application code must explicitly enable the
cache. For more information on the bootloader, see the Using the TMS320DM643x Bootloader Application Report (literature number
SPRAAG0).
(2)
The PLL MODE for Non-Fastboot Modes is fixed as shown in this table; therefore, the PLLMS[2:0] configuration pins have no effect on
the PLL MODE.
(3)
I2C Boot (BOOTMODE[3:0] = 0101b) is only available if the MXI/CLKIN frequency is between 21 MHz to 30 MHz. I2C Boot is not
available for MXI/CLKIN frequencies less than 21 MHz.
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Device Configurations
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