TNETV1644ZDU6 datasheet(85/306 Pages) TI1

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3.4.1.2 Selecting FASTBOOT PLL Multiplier

3.4.1.3 EMIFA Boot Modes

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

Table 3-6, Table 3-7, and Table 3-8 show the PLL multipliers used by the bootloader code during fastboot

(FASTBOOT = 1) and the resulting device frequency. The user is responsible for selecting the bootmode

with the appropriate PLL multiplier for their MXI/CLKIN clock source so that the device speed and PLL

frequency range requirements are met. For the PLLC1 Clock Frequency Ranges, see Table 6-15, PLLC1

Clock Frequency Ranges in Section 6.7.1, PLL1 and PLL2.

The following are guidelines for PLL output frequency and device speed (frequency):

• PLL Output Frequency: (PLLOUT = CLKIN frequency * boot PLL Multiplier) must stay within the

PLLOUT frequency range in Table 6-15, PLLC1 Clock Frequency Ranges.

• Device Frequency: (SYSCLK1) calculated from Table 3-6 and Table 3-7 must not exceed the

SYSCLK1 maximum frequency in Table 6-15, PLLC1 Clock Frequency Ranges.

For example, for a 600-MHz device with a CLKIN = 27 MHz, in order to stay within the PLLOUT

frequency range and SYSCLK1 maximum frequency from Table 6-15, PLLC1 Clock Frequency

Ranges, the user must select a boot mode with a PLL1 multiplier between x15 and x22.

As shown in Table 3-5, Table 3-6, and Table 3-7, there are different types of EMIFA Boot Modes. This

subsection summarizes these types of EMIFA boot modes. For further detailed information, see the Using

the TMS320DM643x Bootloader Application Report (literature number SPRAAG0).

• EMIFA ROM Direct Boot in PLL Bypass Mode (FASTBOOT = 0, BOOTMODE[3:0] = 0100b)

–

The C64x+ fetches the code directly from EMIFA Chip Select 2 Space [EM_CS2] (address

0x4200 0000)

–

The PLL is in Bypass Mode

–

EMIFA is configured as Asynchronous EMIF. The user is responsible for ensuring the desirable

Asynchronous EMIF pins are available through configuration pins AEM[2:0] and AEAW[2:0].

AEM[2:0] must be configured to 001b [8-bit EMIFA (Async) Pinout Mode 1] or 011b [8-bit EMIFA

(Async) Pinout Mode 3].

• EMIFA ROM Fastboot with AIS (FASTBOOT = 1, BOOTMODE[3:0] = 0100b)

–

The C64x+ begins execution from the internal bootloader ROM at address 0x0010 0000.

–

The bootloader code programs PLLC1 to PLL Mode to speed up the boot process. The PLL

multiplier value is determined by the AEM[2:0] and PLLMS[2:0] configurations as shown in

Table 3-6 and Table 3-7.

–

The bootloader code reads code from the EMIFA EM_CS2 space using the application image script

(AIS) format.

–

EMIFA is configured as Asynchronous EMIF. The user is responsible for ensuring the desirable

Asynchronous EMIF pins are available through configuration pins AEM[2:0] and AEAW[2:0].

AEM[2:0] must be configured to 001b [8-bit EMIFA (Async) Pinout Mode 1] or 011b [8-bit EMIFA

(Async) Pinout Mode 3].

• EMIFA ROM Fastboot without AIS: (FASTBOOT = 1, BOOTMODE[3:0] = 1001b)

–

The C64x+ begins execution from the internal bootloader ROM at address 0x0010 0000.

–

The bootloader code programs PLLC1 to PLL Mode to speed up the boot process. The PLL

multiplier value is determined by the AEM[2:0] and PLLMS[2:0] configurations as shown in

Table 3-6 and Table 3-7.

–

The bootloader code then jumps to the EMIFA EM_CS2 space, at which point the C64x+ fetches

the code directly from address 0x4200 0000.

–

EMIFA is configured as Asynchronous EMIF. The user is responsible for ensuring the desirable

Asynchronous EMIF pins are available through configuration pins AEM[2:0] and AEAW[2:0].

AEM[2:0] must be configured to 001b [8-bit EMIFA (Async) Pinout Mode 1] or 011b [8-bit EMIFA

(Async) Pinout Mode 3].

• NAND Flash Boot: (FASTBOOT = 0 or 1, BOOTMODE[3:0] = 0111b)

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