TNETV1644ZDU6 datasheet(144/306 Pages) TI1

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TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Table 3-51. EMIFA/VPSS Sub-Block 1 Configuration Choice B(1)

MAJOR

MINOR

PINMUX SELECTION FIELDS

RESULTING PERIPHERALS/PINS

CONFIG

AEM

OTHERS

EMIFA

VPBE

GPIO

OPTION

8-bit EMIFA (Async)

Cfg Summary

No VENC

9-to-13 GP pins

Pinout Mode 1

VENCSEL = 0

0 = EM_D[7:0]

0 = GP[31, 29:22]

0 = EM_CS2,

RGBSEL = 0

EM_A[4:0],

EM_BA[1:0]

001

CS3SEL = 0,1

1 = EM_CS3

0 = GP[13]

CS4SEL = 0,1

1 = EM_CS4

0 = GP[32]

CS5SEL = 0,1

1 = EM_CS5

0 = GP[33]

1 = VPBECLK, can

VPBECKEN = 0,1

0 = GP[30]

be used by DAC

8-bit EMIFA (Async)

Cfg Summary

8-bit VENC

0-to-4 GP pins

Pinout Mode 1

1 = VCLK,

VENCSEL = 1

1 = EM_D[7:0]

YOUT[7:0]

0 = EM_CS2,

RGBSEL = 0

EM_A[4:0],

001

EM_BA[1:0]

CS3SEL = 0,1,2

1 = EM_CS3

2 = LCD_OE

0 = GP[13]

CS4SEL = 0,1,2

1 = EM_CS4

2 = VSYNC

0 = GP[32]

CS5SEL = 0,1,2

1 = EM_CS5

2 = HSYNC

0 = GP[33]

VPBECKEN = 0,1

1 = VPBECLK

0 = GP[30]

(1)

Italics indicate mandatory setting for a given Minor Configuration option.

144

Device Configurations

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