AS1124

Akros Silicon, inc.

6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA

408.746.9000



www.AkrosSilicon.com

6

 

Typical specifications are not 100% tested. Performance guaranteed by design and/or other correlation methods.

Gate Drive Dynamic Response

PDRV TR, TF

NDRV TR, TF

2.2

2

nS

nS

10% - 90% with CLoad = 1 nF

VPK, peak current sense

threshold voltage at CS

500

600

700

mV

Ipeak=Vpk/Rsense

Max. duty cycle

80

%

Internally limited

Min. duty cycle

6

%

Internally limited

VBN

4.7

V

Low side internal supply voltage; sets

VOH of NDRV.

VBP (relative to VDD48O)

-5

V

High side internal supply voltage; sets

Error amplifier reference

voltage

1.45

1.55

V

Compared to input of the FB pin

Soft start ramp time

2

ms

Conditions: CSS=100nF

COMP source current

30

µA

FB = 0V, COMP=0V

COMP sink current

30

µA

FB = 5V, COMP=5V

Open loop voltage gain

80

dB

Small signal unity gain

bandwidth

5

MHz

COMP connected to FB.

FB leakage (source or sink)

1

µA

0V>FB>4.5V

Local Power Mode

LVMODE Threshold

2.1

2.4

V

LVMODE Hysteresis

100

mV

LVMODE Operating Voltage

10

57

V

Thermal Protection

Thermal shutdown

temperature

165

°C

Above this Temp., the AS1124 is

disabled.

Max. on-die operating

temperature

140

°C

Current reduction temperature

threshold

145

°C

Temperature at which thermal current

reduction is applied

Thermal current reduction

50

%

Thermal current reduction

hysteresis

20

°C

Temperature change required to

restore full operation after thermal

current reduction

Thermal shutdown hysteresis

40

°C

Temperature change required to

restore full operation after thermal

shutdown

Table 5 – Package Thermal Characteristic

Description

Min

Typical

1

Max

Units

Comments

Thermal Resistance, Junction

31

ºC/W

20 lead QFN package

2.4

W

20W Output, (12V output at 1.7A)