AS1124 datasheet(13/21 Pages) ETC2

13 / 21 page

AS1124

Akros Silicon, inc.

6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA

408.746.9000



www.AkrosSilicon.com

Use the following equation to determine typical

classification current:



Tolerance = Maximum of ±1.8mA or ±9%



RCLASS > 63.4kΩ

Local Power Mode

The LV Mode Pin can be used in applications where the

PD appliance draws power from either the Ethernet cable

or a local external DC power source.

When pin11 is

pulled high (> 2.3V), it will open the internal FET switch

while the DC-DC converter remains operational. The local

power should be injected at the VDD48O node, through an

external Schottky diode. Refer to application circuits 8 & 9

for the connection details.

The maximum input voltage at the LVMODE pin should

not exceed 6V. A resistive divider network should be used

to divide down the LVMODE control voltage. Resistor

values will depend on the voltage of the local power

supply. The internal DC-DC converter will operate with

input voltages ranging from 10V to 57V.

The LVMODE pin should only be used when the PD is

configured for class 1-4. The LVMODE pin should not be

used in class 0 applications.

If the LVMODE pin is pulled low, the PD will operate in a

normal fashion, whereby the FET will open when the input

voltage at VDD48I drops below the full power deactivation

threshold.

Figure 15 – AS1124 LVMODE Connection

Idle Mode

In the Idle mode, between Classification and the ON state,

PD Current is limited to monitoring circuitry to detect the

on-state threshold.

ON State

In the ON state, the AS1124 is supplying power. At a

voltage at or above 42V, the PD turns on and full power is

available via the AS1124 DC-DC Controller.

PD CONTROL POWER AND THERMAL

PROTECTIONS

The AS1124 provides the following PD control power and

thermal protections:

Under Voltage Lockout (UVLO)

Current Limit with integrated current sense

Thermal Limit/Protection

Under Voltage Lockout (UVLO)

The AS1124 contains a line Under-Voltage Lockout

(UVLO) circuit. The UVLO circuitry detects conditions

when the supply voltage is too low (less than 36V), and

disconnects the power to protect the PD Inrush Current

Operation.

Inrush limiting maintains the cable voltage above the turn-

off threshold as the input capacitor charges. Also, it helps

prevent the PSE from going into current limit mode.

Current Limit/Current Sense

The Current Limit/Current Sense circuitry minimizes on-

chip temperature peaks by limiting inrush current and

operating current. It monitors the current via an integrated

sense circuit and regulates the gate voltage on an

integrated low-leakage 80V power MOSFET. In addition,

the power MOSFET can be shut down by the PD

Controller subsection or the Thermal Limit Protection

subsection.

Thermal Limit Protection

The AS1124 provides thermal protection for itself by

monitoring die temperature and reducing maximum current

or disconnecting power as needed to prevent pre-set

thermal limits from being exceeded.

Two-stage thermal current limiting is implemented, which

reduces the operating current limit by 50% when the die

temperature reaches 145˚C, and disables the power

MOSFET switch above 165˚C. Normal current limits in

both cases are reapplied when the die temperature returns

to 125˚C.

Table 7 – PoE Requirements

Class

Power

(Watts)

Iclass

Rclass

0.44-12.95

0-4 mA

Pull-up, 1%

0.44-3.84

9-12 mA

280kΩ, 1%

3.84-6.49

17-20 mA

143kΩ, 1%

6.49-12.95

26-30 mA

90.9kΩ, 1%

12.95 – 24W

36-44 mA

63.4kΩ, 1%

]

[

2360

]

[



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

CLASS

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