AS1124 datasheet(16/21 Pages) ETC2

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AS1124

Akros Silicon, inc.

6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA

408.746.9000



www.AkrosSilicon.com

Thermal

De-rating

and

Board

Layout

Considerations

The AS1124 package uses an integral thermal pad to help

dissipate heat from the switch and diode bridge. In higher

power applications, designers must consider thermal

design as an integral part of their systems design and

remove heat via this pad.

Under 802.3af power considerations, the As1124 is

capable

operating

industrial

ambient

air

temperatures, or 85C.

Under increased power, the

operating temperature must be de-rated according to

Figure 6.

The limits for the power de-rating are a max TJ(MAX)=145°C

and a ΘJA=31°C/W, which is achievable in the JEDEC

airflow environment by the 20-pin 5x5mm QFN package.

Figure 18 – Thermal de-rating for high power operation

For adequate heat dissipation, the board layout must

include a ground pad which accomplishes both the ground

connection and dissipates the heat energy generated by

the PD. Thermal vias are used to draw heat away from the

PD package and to transfer it to the backside of the

system PCB

A typical PCB layout for the AS1124 is shown in Figure 19

below.

Figure 17 – AS1124 PCB Footprint

AS1124 PCB Footprint

Thermal Vias

0.31 mm dia.

1.27 mm pitch

9 places

3.80 mm

0.65 mm

0.4

0.5 mm

0.3 mm

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