SPC560D40L1 datasheet(49/90 Pages) STMICROELECTRONICS

49 / 90 page

SPC560D30x, SPC56040Dx

Electrical characteristics

Doc ID 16315 Rev 7

49/90

4.11

Flash memory electrical characteristics

The data flash operation depends strongly on the code flash operation. If code flash is

switched-off, the data flash is disabled.

4.11.1

Program/Erase characteristics

Table 27 shows the program and erase characteristics.

IDDSTDBY

STANDBY mode current(9)

Slow internal RC oscillator

(128 kHz) running

TA = 25 °C

—

100

µA

DTA =55°C

—

DTA = 85 °C

—

180

700

DTA = 105 °C

—

315

1000

PTA = 125 °C

—

560

1700

VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Running consumption does not include I/Os toggling which is highly dependent on the application. The given value is

thought to be a worst case value with all peripherals running, and code fetched from code flash while modify operation

ongoing on data flash. Notice that this value can be significantly reduced by application: switch off not used peripherals

(default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power

mode when possible.

Higher current may be sinked by device during power-up and standby exit. Please refer to in-rush average current on

Table 24.

RUN current measured with typical application with accesses on both flash memory and SRAM.

Only for the “P” classification: Code fetched from SRAM: serial IPs CAN and LIN in loop-back mode, DSPI as Master, PLL

as system clock (3 × Multiplier) peripherals on (eMIOS/CTU/ADC) and running at maximum frequency, periodic SW/WDG

timer reset enabled.

Data flash power down. Code flash in low power. SIRC (128 kHz) and FIRC (16 MHz) on. 10 MHz XTAL clock. FlexCAN: 0

ON (clocked but no reception or transmission). LINFlex: instances: 0, 1, 2 ON (clocked but no reception or transmission),

instance: 3 clocks gated. eMIOS: instance: 0 ON (16 channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz,

instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication). RTC/API ON.PIT ON. STM ON. ADC ON but

no conversion except 2 analog watchdogs.

Only for the “P” classification: No clock, FIRC (16 MHz) off, SIRC (128 kHz) on, PLL off, HPVreg off, ULPVreg/LPVreg on.

All possible peripherals off and clock gated. Flash in power down mode.

When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main regulator

module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures

exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the maximum STOP

specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and

the main regulator will be automatically switched off when the load current is below 6 mA.

Only for the “P” classification: ULPVreg on, HP/LPVreg off, 16 KB SRAM on, device configured for minimum consumption,

all possible modules switched off.

Table 26.

Power consumption on VDD_BV and VDD_HV (continued)

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Typ

Max

Table 27.

Program and erase specifications (code flash)

Symbol

Parameter

Value

Unit

Min

Typ(1)

Initial

max(2)

Max(3)

tdwprogram

CC C Double word (64 bits) program time(4)

—22

500

µs

t16Kpperase CC C 16 KB block preprogram and erase time

—

300

500

5000

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