AD9920ABBCZ datasheet(23/112 Pages) AD

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AD9920A

Rev. B | Page 23 of 112

HORIZONTAL CLAMPING AND BLANKING

The horizontal clamping and blanking pulses of the AD9920A are

fully programmable to suit a variety of applications. Individual

control is provided for CLPOB, PBLK, and HBLK in the different

regions of each field. This allows the dark pixel clamping and

blanking patterns to be changed at each stage of the readout to

accommodate different image transfer timing and high speed

line shifts.

Individual CLPOB and PBLK Patterns

The AFE horizontal timing consists of CLPOB and PBLK, as

shown in Figure 27. These two signals are programmed inde-

pendently using the registers shown in Table 11. The start polarity

for the CLPOB (or PBLK) signal is CLPOBPOL (PBLKPOL), and

the first and second toggle positions of the pulse are CLPOBTOG1

(PBLKTOG1) and CLPOBTOG2 (PBLKTOG2). Both signals

are active low and should be programmed accordingly.

A separate pattern for CLPOB and PBLK can be programmed

for each vertical sequence. As described in the Vertical Timing

Generation section, several V-sequences can be created, each

containing a unique pulse pattern for CLPOB and PBLK.

Figure 57 shows how the sequence change positions divide the

readout field into regions. By assigning a different V-sequence

to each region, the CLPOB and PBLK signals can change with

each change in the vertical timing.

CLPOB and PBLK Masking Areas

Additionally, the AD9920A allows the CLPOB and PBLK signals

to be disabled in certain lines in the field without changing any

of the existing CLPOB pattern settings.

To use CLPOB (or PBLK) masking, the CLPMASKSTART

(PBLKMASKSTART) and CLPMASKEND (PBLKMASKEND)

registers are programmed to specify the start and end lines in

the field where the CLPOB (PBLK) patterns are ignored. The

three sets of start and end registers allow up to three CLPOB

(PBLK) masking areas to be created.

The CLPOB and PBLK masking registers are not specific to a

certain V-sequence; they are always active for any existing field

of timing. During operation, to disable the CLPOB masking

feature, these registers must be set to the maximum value of

0x1FFF or a value greater than the programmed VD length.

Note that to disable CLPOB (or PBLK) masking during power-up,

it is recommended that CLPMASKSTART (PBLKMASKSTART)

be set to 8191 and that CLPMASKEND (PBLKMASKEND) be

set to 0. This prevents any accidental masking caused by register

update events.

Table 11. CLPOB and PBLK Pattern Registers

Length

(Bits)

Range

Description

CLPOBPOL

High/low

Starting polarity of CLPOB for each V-sequence.

PBLKPOL

High/low

Starting polarity of PBLK for each V-sequence.

CLPOBTOG1

0 to 8191 pixel location

First CLPOB toggle position within line for each V-sequence.

CLPOBTOG2

0 to 8191 pixel location

Second CLPOB toggle position within line for each V-sequence.

PBLKTOG1

0 to 8191 pixel location

First PBLK toggle position within line for each V-sequence.

PBLKTOG2

0 to 8191 pixel location

Second PBLK toggle position within line for each V-sequence.

CLPMASKSTART

0 to 8191 line location

CLPOB masking area—starting line within field (maximum of three areas).

CLPMASKEND

0 to 8191 line location

CLPOB masking area—ending line within field (maximum of three areas).

PBLKMASKSTART

0 to 8191 line location

PBLK masking area—starting line within field (maximum of three areas).

PBLKMASKEND

0 to 8191 line location

PBLK masking area—ending line within field (maximum of three areas).

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