AD9920ABBCZ datasheet(84/112 Pages) AD

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AD9920A

Rev. B | Page 84 of 112

ADDITIONAL RESTRICTIONS IN SLAVE MODE

When operating in slave mode, note the following restrictions:

•

The HD falling edge should be located in the same CLI

clock cycle as the VD falling edge or later than the VD

falling edge. The HD falling edge should not be located

within one cycle prior to the VD falling edge.

•

If possible, all start-up serial writes should be performed

with VD and HD disabled. This prevents unknown

behavior caused by partial updating of registers before all

information is loaded. See the Power-Up Sequence for

Master Mode section.

•

There is an inhibit area for SHPLOC to meet the timing

requirement tCLISHP (see Figure 105, Figure 23, and Figure 24).

This restriction is necessary to guarantee a stable reset of

the H-counter in slave mode.

•

When operating the part in slave mode and using a crystal

oscillator to generate CLI, it can be very difficult to meet

the tHDCLI specification because there is no phase control

over the oscillator output. Special care must be taken to

meet the critical tHDCLI specification when operating in this

condition.

CLI

tCLIDLY

35.5 CYCLES

H-COUNTER

RESET

SHPLOC

INTERNAL

H-COUNTER

(PIXEL COUNTER)

tVDHD

SHDLOC

INTERNAL

tHDCLI

tCLISHP

tSHPINH

tCONV

NOTES:

1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, AND THEN LATCHED BY SHPLOC (INTERNAL SAMPLING EDGE).

2. INTERNAL H-COUNTER IS ALWAYS RESET 35.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE AT SHDLOC (INTERNAL SAMPLING EDGE).

3. DEPENDING ON THE VALUE OF SHPLOC, H-COUNTER RESET CAN OCCUR 36 OR 37 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.

4. SHPLOC = 32, SHDLOC = 0 IS SHOWN. IN THIS CASE, THE H-COUNTER RESET OCCURS 36 CLI RISING EDGES AFTER HD FALLING EDGE.

5. HD FALLING EDGE SHOULD OCCUR COINCIDENT WITH THE VD FALLING EDGE (WITHIN SAME CLI CYCLE) OR AFTER THE VD FALLING EDGE. HD FALLING

EDGE SHOULD NOT OCCUR WITHIN ONE CYCLE IMMEDIATELY BEFORE THE VD FALLING EDGE.

Figure 105. External VD/HD and Internal H-Counter Synchronization, Slave Mode

1HBLKTOG1

(60 – 36) = 24

2HBLKTOG2

100

(100 – 36) = 64

3CLPOBTOG1

103

(103 – 36) = 67

4CLPOBTOG2

112

(112 – 36) = 76

MASTER MODE

SLAVE MODE

CLPOB

PIXEL NO.

112

103

100

Figure 106. Example of Slave Mode Register Settings to Obtain Desired Toggle Positions

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