AD9920ABBCZ datasheet(73/112 Pages) AD

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AD9920A

Rev. B | Page 73 of 112

MANUAL SHUTTER OPERATION USING

ENHANCED SYNC MODES

The AD9920A also supports an external signal to control exposure,

using the SYNC input. Generally, the SYNC input is used as an

asynchronous reset signal during master mode operation. When

the enhanced SYNC mode is enabled, the SYNC input provides

additional control of the exposure operation.

Normal SYNC Mode (Mode 1)

By default, the SYNC input is used in master mode to synchronize

the internal counters of the AD9920A with external timing. The

horizontal, vertical, and field designator signals are reset by the

rising edge of the SYNC pulse. Figure 94 shows how this mode

operates, highlighting the behavior of the mode field designator.

Enhanced SYNC Modes (Mode 2 and Mode 3)

The enhanced SYNC modes can be used to accommodate unique

synchronization requirements during exposure operations. In

SYNC Mode 2, the V and VSG outputs are suspended and the

VD output is masked. The V-outputs are held at the dc value

established by the V-Sequence 0 start polarities. There is no SCP

operation, but the H-counter is still enabled. Finally, the AFE

sampling clocks, HD, H/RG, CLPOB, and HBLK, are operational

and use V-Sequence 0 behavior. See Figure 95 for more details.

To enable the enhanced SYNC modes, set the ENH_SYNC_EN

SYNC Mode 3 uses all the features of Mode 2, but the V-outputs

are continuous through the SYNC pulse interval. VD control

pulses are masked during the SYNC interval, and the HD pulse

can also be masked, if required (see Figure 96).

It is important to note that in both enhanced modes, the SYNC

pulse resets the counters at both the falling edge and the rising

edge of the SYNC pulse.

When using SYNC Mode 2 or SYNC Mode 3, VD-updated

registers, such as PRIMARY_ACTION, are not updated during

the SYNC interval, and the SCP0 function is ignored and held

at 0 (see Figure 97).

When using either SYNC Mode 2 or SYNC Mode 3, both the

rising and falling edges increment the internal field designator;

therefore, the new register data takes effect and VTP information is

updated to new SEQ0 data. However, this does not occur if the

mode register is creating an output of one field. In that case, the

region, sequence, and group information does not change (see

Figure 98).

Shutter Operation in SLR Mode

The following steps are shown in Figure 99.

To turn on VSUB, write to the appropriate GP registers to

trigger VSUB and start the manual exposure (PRIMARY_

ACTION = 5). This change takes effect after the next VD.

SUBCK is suppressed during the exposure and readout

phases.

To turn on MSHUT during the interval between the next

VD and SYNC, write to the appropriate GP register. When

MSHUT is in the on position, it has line and pixel control.

This change takes effect on the SYNC falling edge because

there is an internal VD.

If the mode register is programmed to cycle through

multiple fields (5, 7, 3, 5, 7, 3, …, in this example), the

internal field designator increments. If the mode register

is not required to increment, set up the mode register such

that it outputs only one field. This prevents the mode

counter from incrementing during the SYNC interval.

Write to the manual readout trigger to begin the manual

readout (PRIMARY_ACTION = 6). Write to the appropriate

GP registers to trigger MSHUT to toggle low at the end of

the exposure. This change takes effect on the SYNC rising

edge during readout. Because VD register update is disabled,

the trigger takes effect on the SYNC rising edge. The MSHUT

falling edge is aligned with the SYNC rising edge. Because

the MSHUT falling edge is aligned with VD, it may be

necessary to insert a dummy VD to delay the readout.

Because the internal exposure counter (the primary counter) is

not used during manual SYNC mode operation and the VD

of the GP signals for VSUB, MSHUT, and STROBE edges while

SYNC is low.

Serial Registers for Enhanced SYNC Modes

SYNC Mode 2 and SYNC Mode 3 are controlled using the

registers listed in Table 47. These registers are located at

Address 0x13, Bits[6:3].

Table 47. Registers for Enhanced SYNC Modes

Length

(Bits)

Description

ENH_SYNC_EN

High active to enable masking

(default low)

SYNC_MASK_V

High active to enable masking

(default high)

SYNC_MASK_VD

High active to enable masking

(default high)

SYNC_MASK_HD

High active to enable masking

(default low)

AD9920ABBCZ Datasheet(PDF) 73 Page - Analog Devices

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