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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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AD9920ABBCZ Datasheet(PDF) 83 Page - Analog Devices |
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AD9920ABBCZ Datasheet(HTML) 83 Page - Analog Devices |
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83 / 112 page  AD9920A Rev. B | Page 83 of 112 POWER-DOWN SEQUENCE FOR MASTER AND SLAVE MODES 1. Write 0 to the appropriate bit in the GPO_OUTPUT_EN register (Address 0x7A) to set the appropriate VDR_EN control signal low. 2. The next VD edge updates Address 0x7A, causing the VDR_EN signal to go low and disabling the V-driver outputs. If operating in slave mode, turn off VD and HD after VDR_EN switches low. 3. Write 0x03 to the AFE standby register (Address 0x00) to place the AD9920A into Standby3 mode. 4. Power down the V-driver supplies. 5. Power down the 3 V and 1.8 V supplies. 4 0V 1 5 3 VM VL (SUBCK) 0V 2 SERIAL WRITES VD HD H-CLOCKS VDR_EN V1 TO V15 XSUBCK POWER SUPPLIES VH SUPPLY VL SUPPLY +1.8V SUPPLIES +3V SUPPLIES VM SUPPLY Figure 104. Recommended Power-Down Sequence, Master or Slave Mode |
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