MRF49XA-ISLASHT datasheet(9/102 Pages) MICROCHIP

9 / 102 page

Preliminary

DS70590C-page 9

MRF49XA

2.0

HARDWARE DESCRIPTION

The MRF49XA is an integrated, single chip ISM Band

Sub-GHz Transceiver. A simplified architectural block

diagram of the MRF49XA is shown in Figure 2-1.

The frequency synthesizer is clocked by an external

10 MHz crystal and generates the 433, 868 and 915

MHz radio frequency. The receiver with a Zero-IF

architecture consists of the following components:

•LNA

• Down Conversion Mixers

• Channel Filters

• Baseband Limiting Amplifiers

• Receiver Signal Strength Indicator

The transmitter with a direct conversion architecture

has a typical output power of +7 dBm. An internal

transmit/receive switch combines the transmitter and

receiver circuits into differential RFP and RFN pins.

These pins are connected to the impedance matching

circuitry (Balun) and to the external antenna connected

to the device.

The device operates in the low-voltage range of 2.2V–

3.8V, and in Sleep mode, it operates at a very low-current

state, typically 0.3 μA.

The quality of the data is checked or validated using the

RSSI and DQI blocks built into the transceiver. Data is

buffered in transmitter registers and receiver FIFOs.

The AFC feature allows the use of a low-accuracy and

low-cost crystal. The CLKOUT is used to clock the

external controller. The transceiver is controlled through

4-wire

SPI,

interrupt

(INT/DIO

and

IRO),

FSK/DATA/FSEL, RCLKOUT/FCAP/FINT and RESET

pins. See Table 2-1 for pin details.

The MRF49XA supports the following feature blocks:

• Clock Generation

• Data Filtering and Amplification

• Data Pattern Recognition and Timing

• Data Processing and Storage

• Independent Transmit and Receiver FIFO Buffers

• Registers

These features reduce the processing load, and hence,

allows the use of low-cost 8-bit microcontrollers for data

processing.

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