MRF49XA-ISLASHT datasheet(29/102 Pages) MICROCHIP

29 / 102 page

Preliminary

DS70590C-page 29

MRF49XA

BBFCREG: BASEBAND FILTER CONFIGURATION REGISTER (POR: 0xC22C)

W-1

W-0

W-1

W-0

CCB<15:8>

bit 15

bit 8

W-0

W-1

W-0

W-1

W-0

ACRLC

MCRLC

FTYPE

DQTI<2:0>

bit 7

bit 0

Legend:

r = reserved bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-8

CCB<15:8>: Command Code bits

The command code bits (11000010b) are serially sent to the microcontroller to identify the bits to be

written in the BBFCREG.

bit 7

ACRLC: Automatic Clock Recovery Lock Control bit

1 = Configures the clock recovery lock control as automatic. In this setting, the clock recovery starts

in Fast mode and automatically switches to Slow mode after locking

0 = Clock recovery lock is controlled in Manual mode

bit 6

MCRLC: Manual Clock Recovery Lock Control bit

1 = Configures the clock recovery lock control to Fast mode. Fast mode requires a preamble of at least

6-8 bits to determine the clock rate and then it locks.

0 = Configures the clock recovery lock control to Slow mode. Slow mode takes a bit longer period and

requires a preamble of at least 12-16 bits to determine the clock rate and then it locks. Slow mode

requires more accurate bit timing. See Register 2-12 for the relationship between data rate and

clock recovery.

bit 5

Reserved: Write as ‘1’

bit 4

FTYPE: Filter Type bit

1 = Configures the baseband filter as an analog RC low-pass filter

0 = Configures the baseband filter as a digital filter(1)

bit 3

Reserved: Write as ‘1’

bit 2-0

DQTI<2:0>: Data Quality Threshold Indicator bits

The threshold parameter for the DQI should be set to less than four to report good signal quality if the

bit rate is close to the deviation. Usually, if the data rate falls less than the deviation, a higher threshold

parameter is permitted and might report a good signal quality(2).

Note 1: The digital filter is a digital version of a simple RC low-pass filter followed by a comparator with hysteresis.

The time constant for the digital filter is automatically calculated based on the bit rate set in the DRSREG.

The bit rate in this mode should not exceed 115 kbps. In analog RC filter, the demodulator output is fed to

the RCLKOUT/FCAP/FINT pin over a 10 kΩ resistor. The filter cutoff frequency is set by the external

capacitor connected to this pin and VSS. Table 2-6 shows the optimum filter capacitor values for different

data rates.

2: The DQI parameter is calculated using Equation 2-3. The DQI parameter in BBFCREG should be chosen

according to the following rules:

- The parameter should be > 4, otherwise, noise might be treated as a valid FSK signal.

- The maximum value is 7.

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