MRF49XA-ISLASHT datasheet(70/102 Pages) MICROCHIP

70 / 102 page

MRF49XA

DS70590C-page 70

Preliminary

3.18

RX FIFO Buffered Data Read

In the Receive Operating mode, the incoming data is

clocked into a 16-bit FIFO buffer. The receive pin

function configuration required for the FIFO operation

is given in Table 3-4. The FIFOEN bit is in the

GENCREG register and enables the receive FIFO. The

receiver starts to fill the FIFO when the FINTDIO bit and

the synchronous pattern recognition circuit indicates

the potential real incoming data. This prevents the

FIFO from being filled with noise and avoids the

overloading on the external microcontroller.

The internal synchronous pattern and the pattern

length are user-programmable. If the Chip Select (CS)

pin is low, the data bits on the SDI pin are shifted into

the device on the rising edge of the clock on the SCK

pin. The serial interface is initialized every time if the

CS signal is high. Figure 3-18 shows a simple receiver

FIFO read over SPI lines.

In general, MRF49XA registers are read only. The

RXFIFO and the chip status can be read. During write

only appropriate byte is written to the desired register.

Hence it is not desired to read/write all registers and

there is no way reading back any of the other registers.

To test the SPI interface lines, the best is to set the LBD

(Low Battery Detector) threshold below the actual VDD

and the device must generate an interrupt.

FIGURE 3-18:

RECEIVER FIFO READ

SDO

SCK

MSB

SDI

LSB

TXRXFIFO

Received Bits Out

Note: The transceiver is in Receive (RX) mode when the RXCEN bit is set using the PMCREG.

(TX/RX mode)

MRF49XA-I/T Datasheet(PDF) 70 Page - Microchip Technology