MRF49XA-ISLASHT datasheet(32/102 Pages) MICROCHIP

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MRF49XA

DS70590C-page 32

Preliminary

FIFORSTREG: FIFO AND RESET MODE CONFIGURATION REGISTER

(POR: 0xCA80)

W-1

W-0

W-1

W-0

W-1

W-0

CCB<15:8>

bit 15

bit 8

W-1

W-0

FFBC<3:0>

SYCHLEN

FFSC

FSCF

DRSTM

bit 7

bit 0

Legend:

r = reserved bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-8

CCB<15:8>: Command Code bits

The command code bits (11001010b) are serially sent to the microcontroller to identify the bits to be

written in the FIFORSTREG.

bit 7-4

FFBC<3:0>: FIFO Fill Bit Count bits

Sets the received bits before generating an external interrupt to the host microcontroller to indicate the

receive FIFO is ready to be read. The maximum fill level is 15(1).

bit 3

SYCHLEN: Synchronous Character Length bit

This bit sets the synchronous character length to byte or word long.(2)

1 = Byte long. User-programmable SCL0 byte is used.

0 = Word long. The character is composed of the SCL1 and SCL0 bytes. The SCL1 byte value is fixed

and is not configurable. The SCL0 byte value is user-programmable through the SYNBREG.

bit 2

FFSC: FIFO Fill Start Condition bit

This bit sets the condition at which the FIFO starts filling with data.

1 = The FIFO will continuously fill irrespective of noise or good data

0 = The FIFO will fill when it recognizes the synchronous character pattern as defined internally

bit 1

FSCF: FIFO Synchronous Character Fill bit

1 = The FIFO starts filling with data when it detects the synchronous character pattern as defined in

the FFSC bit

0 = The FIFO fill stops

To restart the synchronous character pattern recognition, just clear and set this bit(2).

bit 0

DRSTM: Disable (Sensitive) Reset mode bit

1 = Disables(3)

0 = Enables System Reset for any glitches above 0.2V in the power supply

Note 1: On register overrun, the data will be lost. Therefore, the developer must take into account the processing

time required to read-out data before a register overrun. It is recommended to set the fill value to half of

the desired number of bits to be read to ensure sufficient time for additional processing. See Register 2-1

for the description of the TXRXFIFO and TXUROW bits, and Register 2-9 for details on polling and

interrupt driven FIFO reads from the SPI bus.

2: For synchronous character length selection, see Table 2-8.

3: For Reset mode selection, see Table 2-9.

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