320 datasheet(60/82 Pages) INTEL

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Datasheet

Pin Listing and Signal Descriptions

SLP#

Input

SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter

the Sleep state. During Sleep state, the processor stops providing internal clock

signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.

Processors in this state will not recognize snoops or interrupts. The processor

will recognize only assertion of the RESET# signal, and de-assertion of SLP#. If

SLP# is de-asserted, the processor exits Sleep state and returns to Stop-Grant

state, restarting its internal clock signals to the bus and processor core units.

SMI#

Input

SMI# (System Management Interrupt) is asserted asynchronously by system

logic. On accepting a System Management Interrupt, the processor saves the

current state and enter System Management Mode (SMM). An SMI

Acknowledge transaction is issued, and the processor begins program execution

from the SMM handler.

If SMI# is asserted during the de-assertion of RESET#, the processor will tristate

its outputs.

STPCLK#

Input

STPCLK# (Stop Clock), when asserted, causes the processor to enter a low

power Stop-Grant state. The processor issues a Stop-Grant Acknowledge

transaction, and stops providing internal clock signals to all processor core units

except the FSB and APIC units. The processor continues to snoop bus

transactions and service interrupts while in Stop-Grant state. When STPCLK# is

de-asserted, the processor restarts its internal clock to all units and resumes

execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#

is an asynchronous input.

TCK

Input

TCK (Test Clock) provides the clock input for the processor Test Bus (also known

as the Test Access Port).

TDI

Input

TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDO

Output

TDO (Test Data Out) transfers serial test data out of the processor. TDO

provides the serial output needed for JTAG specification support.

TESTHI[12:0]

Input

TESTHI[12:0] must be connected to a VCC power source through a resistor for

proper processor operation. See Section 2.5 for more details.

THERMDA

Other

Thermal Diode Anode. See Section 5.2.6.

THERMDC

Other

Thermal Diode Cathode. See Section 5.2.6.

THERMTRIP#

Output

In the event of a catastrophic cooling failure, the processor will automatically

shut down when the silicon has reached a temperature approximately 20 °C

above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the

processor junction temperature has reached a level beyond which permanent

silicon damage may occur. Upon assertion of THERMTRIP#, the processor will

shut off its internal clocks (thus halting program execution) in an attempt to

reduce the processor junction temperature. To protect the processor, its core

voltage (VCC) must be removed following the assertion of THERMTRIP#. Driving

of the THERMTRIP# signal is enabled within 10

µs of the assertion of

PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated,

THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-

assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the

processor’s junction temperature remains at or above the trip level,

THERMTRIP# will again be asserted within 10

µs of the assertion of

PWRGOOD.

TMS

Input

TMS (Test Mode Select) is a JTAG specification support signal used by debug

tools.

TRDY#

Input

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to

receive a write or implicit writeback data transfer. TRDY# must connect the

appropriate pins of all FSB agents.

TRST#

Input

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be

driven low during power on Reset.

Table 4-3. Signal Description (Sheet 7 of 8)

Name

Type

Description

320 Datasheet(PDF) 60 Page - Intel Corporation

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