MPC5634MF0MMGA6 datasheet(82/118 Pages) FREESCALE

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MPC5634M Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Electrical characteristics

Freescale Semiconductor

fUL

Frequency un-LOCK range

—

–18

% fsys

fCS

fDS

Modulation Depth

Center spread

±0.25

±4.0

%fsys

Down Spread

–0.5

–8.0

fMOD

Modulation frequency18

—

100

kHz

1 All values given are initial design targets and subject to change.

2 Considering operation with PLL not bypassed.

3 f

VCO is calculated as follows:

— In Legacy Mode fVCO = (fcrystal/(PREDIV+1))*(4*(MFD+4))

— In Enhanced Mode fvco = (Fcrystal/(EPREDIV+1))*(EMFD+4)

4 All internal registers retain data at 0 Hz.

5 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.

6 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the f

LOR

window.

7 f

VCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced

mode.

8 This value is determined by the crystal manufacturer and board design.

9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

SYS.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER

percentage for a given interval.

10 Proper PC board layout procedures must be followed to achieve specifications.

11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C

JITTER and either

fCS or fDS (depending on whether center spread or down spread modulation is enabled).

12 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this

PLL, load capacitors should not exceed these limits.

13 Proper PC board layout procedures must be followed to achieve specifications.

14 This parameter is guaranteed by design rather than 100% tested.

15 Vxtal range is preliminary and subject to change pending characterization data.

16 V

IHEXT cannot exceed VRC33 in external reference mode.

17 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR).

18 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50kHz.

Table 24. PLLMRFM electrical specifications1

(VDDPLL =1.14 V to 1.32 V, VSS = VSSPLL = 0 V, TA = TL to TH) (continued)

Symbol

Parameter

Conditions

Value

Unit

min

max

MPC5634MF0MMGA6 Datasheet(PDF) 82 Page - Freescale Semiconductor, Inc

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