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MPC5634MF0MMGA6 Datasheet(PDF) 53 Page - Freescale Semiconductor, Inc |
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MPC5634MF0MMGA6 Datasheet(HTML) 53 Page - Freescale Semiconductor, Inc |
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53 / 118 page  Pinout and signal description MPC5634M Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice Freescale Semiconductor 53 CAL_RD_WR Calibration Bus RD_WR indicates whether the current transaction is a read access or a write access. CAL_TS_ALE Calibration Bus The Transfer Start signal (TS) is asserted by the MPC5634M to indicate the start of a transfer. The Address Latch Enable (ALE) signal is used to demultiplex the address from the data bus. CAL_EVTO Calibration Bus Nexus Event Out CAL_MCKO Calibration Bus Nexus Message Clock Out NEXUSCFG Nexus/Calibration Bus Nexus/Calibration Bus selector eMIOS[0:23] eMIOS eMIOS I/O channels AN[0:39] eQADC Single-ended analog inputs for analog-to-digital converter FCK eQADC eQADC free running clock for eQADC SSI. MA[0:2] eQADC These three control bits are output to enable the selection for an external Analog Mux for expansion channels. REFBYPC eQADC Bypass capacitor input SDI eQADC Serial data in SDO eQADC Serial data out SDS eQADC Serial data select VRH eQADC Voltage reference high input VRL eQADC Voltage reference low input SCI_A_RX SCI_B_RX eSCI_A - eSCI_B eSCI receive SCI_A_TX SCI_B_TX eSCI_A - eSCI_B eSCI transmit ETPU_A[0:31] eTPU eTPU I/O channel CAN_A_TX CAN_C_TX FlexCan_A - FlexCAN_C FlexCAN transmit CAN_A_RX CAN_C_RX FlexCAN_A - FlexCAN_C FlexCAN receive JCOMP JTAG Enables the JTAG TAP controller. TCK JTAG Clock input for the on-chip test and debug logic. TDI JTAG Serial test instruction and data input for the on-chip test and debug logic. TDO JTAG Serial test data output for the on-chip test logic. TMS JTAG Controls test mode operations for the on-chip test and debug logic. Table 5. Signal details (continued) Signal Module or Function Description |
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