LTC2401CMS datasheet(23/32 Pages) LINER

23 / 32 page

LTC2401/LTC2402

reference, on a regular FR-4 board, signal propagation

velocity is approximately 183ps/inch for internal traces

and 170ps/inch for surface traces. Thus, a driver gener-

ating a control signal with a minimum transition time of

1ns must be connected to the converter pin through a

trace shorter than 2.5 inches. This problem becomes

particularly difficult when shared control lines are used

and multiple reflections may occur. The solution is to

carefully terminate all transmission lines close to their

characteristic impedance.

Parallel termination near the LTC2401/LTC2402 pin will

eliminate this problem but will increase the driver power

dissipation. A series resistor between 27

Ω and 56Ω

placed near the driver or near the LTC2401/LTC2402 pin

will also eliminate this problem without additional power

dissipation. The actual resistor value depends upon the

trace impedance and connection topology.

Driving the Input and Reference

The analog input and reference of the typical delta-sigma

analog-to-digital converter are applied to a switched ca-

pacitor network. This network consists of capacitors

switching between the analog input (VIN), ZSSET (Pin 5)

and FSSET (Pin 2). The result is small current spikes seen

at both VIN and VREF. A simplified input equivalent circuit

is shown in Figure 15.

The key to understanding the effects of this dynamic

input current is based on a simple first order RC time

constant model. Using the internal oscillator, the

LTC2401/LTC2402’s internal switched capacitor network

is clocked at 153,600Hz corresponding to a 6.5

µs sam-

pling period. Fourteen time constants are required each

time a capacitor is switched in order to achieve 1ppm

settling accuracy.

Therefore, the equivalent time constant at VIN and VREF

should be less than 6.5

µs/14 = 460ns in order to achieve

1ppm accuracy.

Input Current (VIN)

If complete settling occurs on the input, conversion results

will be uneffected by the dynamic input current. If the

settling is incomplete, it does not degrade the linearity

performance of the device. It simply results in an offset/

full-scale shift, see Figure 16. To simplify the analysis of

input dynamic current, two separate cases are assumed:

large capacitance at VIN (CIN > 0.01µF) and small capaci-

tance at VIN (CIN < 0.01µF).

APPLICATIO S I FOR ATIO

FSSET

CH0/CH1

VCC

RSW

AVERAGE INPUT CURRENT:

IIN = 0.25(VIN – 0.5 • VREF)fCEQ

IREF(LEAK)

VCC

RSW

CEQ

2.5pF (TYP)

RSW

IIN(LEAK)

IIN

24012 F15

IIN(LEAK)

SWITCHING FREQUENCY

f = 153.6kHz FOR INTERNAL OSCILLATOR (fO = LOGIC LOW OR HIGH)

f = fEOSC FOR EXTERNAL OSCILLATORS

ZSSET

Figure 15. LTC2401/LTC2402 Equivalent Analog Input Circuit

ZSSET

TUE

VIN

24012 F16

FSSET

Figure 16. Offset/Full-Scale Shift

If the total capacitance at VIN (see Figure 17) is small

(< 0.01

µF), relatively large external source resistances (up

to 20k for 20pF parasitic capacitance) can be tolerated

without any offset/full-scale error. Figures 18 and 19 show

a family of offset and full-scale error curves for various

small valued input capacitors (CIN < 0.01µF) as a function

of input source resistance.

For large input capacitor values (CIN > 0.01µF), the input

spikes are averaged by the capacitor into a DC current. The

gain shift becomes a linear function of input source

LTC2401CMS Datasheet(PDF) 23 Page - Linear Technology

LTC2401CMS Datasheet(HTML) 23 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Descarga

Enlace URL