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LTC2401/LTC2402

In addition, the CS signal can be used to trigger a new

conversion cycle before the entire serial data transfer has

been completed. The LTC2401/LTC2402 will abort any

serial data transfer in progress and start a new conversion

cycle anytime a LOW-to-HIGH transition is detected at the

CS pin after the converter has entered the data output state

(i.e., after the first rising edge of SCK occurs with CS = 0).

Finally, CS can be used to control the free-running modes

of operation, see Serial Interface Timing Modes section.

Grounding CS will force the ADC to continuously convert

at the maximum output rate selected by FO. Tying a

capacitor to CS will reduce the output rate and power

dissipation by a factor proportional to the capacitor’s

value, see Figures 12 to 14.

SERIAL INTERFACE TIMING MODES

The LTC2401/LTC2402’s 3-wire interface is SPI and

MICROWIRE compatible. This interface offers several

flexible modes of operation. These include internal/exter-

nal serial clock, 2- or 3-wire I/O, single cycle conversion

and autostart. The following sections describe each of

these serial interface timing modes in detail. In all these

cases, the converter can use the internal oscillator (FO =

LOW or FO = HIGH) or an external oscillator connected to

the FO pin. Refer to Table 4 for a summary.

External Serial Clock, Single Cycle Operation

(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 5.

The serial clock mode is selected on the falling edge of CS.

To select the external serial clock mode, the serial clock pin

(SCK) must be LOW during each CS falling edge.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

While CS is pulled LOW, EOC is output to the SDO pin. EOC

= 1 while a conversion is in progress and EOC = 0 if the

device is in the sleep state. Independent of CS, the device

automatically enters the low power sleep state once the

conversion is complete.

When the device is in the sleep state (EOC = 0), its

conversion result is held in an internal static shift register.

The device remains in the sleep state until the first rising

edge of SCK is seen while CS is LOW. Data is shifted out

the SDO pin on each falling edge of SCK. This enables

external circuitry to latch the output on the rising edge of

SCK. EOC can be latched on the first rising edge of SCK

and the last bit of the conversion result can be latched on

the 32nd rising edge of SCK. On the 32nd falling edge of

SCK, the device begins a new conversion. SDO goes HIGH

(EOC = 1) indicating a conversion is in progress.

At the conclusion of the data cycle, CS may remain LOW

and EOC monitored as an end-of-conversion interrupt.

Alternatively, CS may be driven HIGH setting SDO to Hi-Z.

As described above, CS may be pulled LOW at any time in

order to monitor the conversion status.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first rising edge and the

32nd falling edge of SCK, see Figure 6. On the rising edge

Table 4. LTC2401/LTC2402 Interface Timing Modes

Conversion

Data

Connection

SCK

Cycle

Output

and

Configuration

Source

Control

Waveforms

External SCK, Single Cycle Conversion

External

CS and SCK

Figures 5, 6

External SCK, 2-Wire I/O

External

SCK

Figure 7

Internal SCK, Single Cycle Conversion

Internal

↓

Figures 8, 9

Internal SCK, 2-Wire I/O, Continuous Conversion

Internal

Continuous

Internal

Figure 10

Internal SCK, Autostart Conversion

Internal

CEXT

Internal

Figure 11

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