LTC2401CMS datasheet(18/32 Pages) LINER

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LTC2401/LTC2402

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output

to the SDO pin. EOC = 1 while a conversion is in progress

and EOC = 0 if the device is in the sleep state.

When testing EOC, if the conversion is complete (EOC = 0),

the device will exit the sleep state and enter the data output

state if CS remains LOW. In order to prevent the device

from exiting the low power sleep state, CS must be pulled

HIGH before the first rising edge of SCK. In the internal

SCK timing mode, SCK goes HIGH and the device begins

outputting data at time tEOCtest after the falling edge of CS

(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW

during the falling edge of EOC). The value of tEOCtest is 23µs

if the device is using its internal oscillator (F0 = logic LOW

or HIGH). If FO is driven by an external oscillator of

frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled

HIGH before time tEOCtest, the device remains in the sleep

state. The conversion result is held in the internal static

shift register.

If CS remains LOW longer than tEOCtest, the first rising

edge of SCK will occur and the conversion result is serially

shifted out of the SDO pin. The data output cycle begins on

this first rising edge of SCK and concludes after the 32nd

rising edge. Data is shifted out the SDO pin on each falling

edge of SCK. The internally generated serial clock is output

to the SCK pin. This signal may be used to shift the

conversion result into external circuitry. EOC can be

latched on the first rising edge of SCK and the last bit of the

conversion result on the 32nd rising edge of SCK. After the

32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays

HIGH, and a new conversion starts.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first and 32nd rising edge

of SCK, see Figure 9. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

new conversion. This is useful for systems not requiring

all 32 bits of output data, aborting an invalid conversion

cycle, or synchronizing the start of a conversion. If CS is

pulled HIGH while the converter is driving SCK LOW, the

APPLICATIO S I FOR ATIO

SDO

SCK

(INTERNAL)

MSB

EXR

SIG

CH0/CH1

BIT 0

LSB24

BIT 4

TEST EOC

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

2400 F08

<tEOCtest

VCC

10k

Hi-Z

TEST EOC

VCC

FSSET

ZSSET

SCK

CH1

SDO

GND

REFERENCE VOLTAGE

ZSSET + 0.1V TO VCC

0V TO FSSET – 100mV

CH0

= INTERNAL OSC/50Hz REJECTION

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

µF

110

2.7V TO 5.5V

LTC2402

VCC

ANALOG INPUT RANGE

ZSSET – 0.12VREF TO

FSSET + 0.12VREF

(VREF = FSSET – ZSSET)

Figure 8. Internal Serial Clock, Single Cycle Operation

LTC2401CMS Datasheet(PDF) 18 Page - Linear Technology

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