LTC2401CMS datasheet(17/32 Pages) LINER

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LTC2401/LTC2402

of CS, the device aborts the data output state and imme-

diately initiates a new conversion. This is useful for

systems not requiring all 32 bits of output data, aborting

an invalid conversion cycle or synchronizing the start of a

conversion.

External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface. The

conversion result is shifted out of the device by an exter-

nally generated serial clock (SCK) signal, see Figure 7. CS

may be permanently tied to ground (Pin 6), simplifying the

user interface or isolation barrier.

The external serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately 0.5ms after VCC exceeds 2.2V. The level

applied to SCK at this time determines if SCK is internal or

external. SCK must be driven LOW prior to the end of POR

in order to enter the external serial clock timing mode.

Since CS is tied LOW, the end-of-conversion (EOC) can

be continuously monitored at the SDO pin during the

convert and sleep states. EOC may be used as an inter-

rupt to an external controller indicating the conversion

result is ready. EOC = 1 while the conversion is in

progress and EOC = 0 once the conversion enters the low

power sleep state. On the falling edge of EOC, the conver-

sion result is loaded into an internal static shift register.

The device remains in the sleep state until the first rising

edge of SCK. Data is shifted out the SDO pin on each

falling edge of SCK enabling external circuitry to latch

data on the rising edge of SCK. EOC can be latched on the

first rising edge of SCK. On the 32nd falling edge of SCK,

SDO goes HIGH (EOC = 1) indicating a new conversion

has begun.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 8.

In order to select the internal serial clock timing mode, the

serial clock pin (SCK) must be floating (Hi-Z) or pulled

HIGH prior to the falling edge of CS. The device will not

enter the internal serial clock mode if SCK is driven LOW

on the falling edge of CS. An internal weak pull-up resistor

is active on the SCK pin during the falling edge of CS;

therefore, the internal serial clock timing mode is auto-

matically selected if SCK is not externally driven.

Figure 7. External Serial Clock, CS = 0 Operation

APPLICATIO S I FOR ATIO

EOC

BIT 31

SDO

SCK

(EXTERNAL)

MSB

EXR

SIG

CH0/CH1

BIT 0

LSB24

BIT 4

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

SLEEP

DATA OUTPUT

CONVERSION

24012 F07

CONVERSION

VCC

FSSET

ZSSET

SCK

CH1

SDO

GND

REFERENCE VOLTAGE

ZSSET + 0.1V TO VCC

0V TO FSSET – 100mV

CH0

= INTERNAL OSC/50Hz REJECTION

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

µF

110

2-WIRE SERIAL I/O

2.7V TO 5.5V

LTC2402

VCC

ANALOG INPUT RANGE

ZSSET – 0.12VREF TO

FSSET + 0.12VREF

(VREF = FSSET – ZSSET)

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