HIP2103, HIP2104

6. Application Examples

FN8276 Rev.2.0

Page 22 of 30

Feb 25, 2021

In the unlikely event that the negative transient exceeds -10V, there are several ways of reducing the negative

amplitude of this transient. If the bridge FETs are turned off more slowly to reduce di/dt, the amplitude is reduced

but at the expense of more switching losses in the FETs. Careful PCB design also reduces the value of the

parasitic inductance. However, in extreme cases, these two solutions by themselves may not be sufficient.

Figure 25 shows a simple method for clamping the negative transient. Two series connected, fast 1A PN junction

diodes are connected between HS and VSS as shown. It is important that these diodes are placed as close as

possible to the HS and VSS pins to minimize the parasitic inductance of this current path between the two pins.

Two diodes in series are required because they are in parallel with the body diode of the low-side FET. If only one

diode is used for the clamp, it conducts some of the negative load current that is flowing in the body diode of the

low-side FET.

An alternative to the two series connected diodes is one diode and a resistor (Figure 26 on page 23). In this case,

it is necessary to limit the current in the diode with a small value resistor, RHS, connected between the phase node

of the 1/2 bridge and the HS pin. Observe that RHS is effectively in series with the HO output and serves as a peak

current limiting gate resistor on HO.

Figure 24. Parasitic Inductance on HS Node

Figure 25. Two Clamping Diodes to Suppress Negative Transients

VSS

HS

LO

HO

Inductive

Load

+

-

+

-

HB

CBOOT

VSS

HS

LO

HO

Inductive

Load

HB

CBOOT

1V

-

+