HIP2103, HIP2104

5. Functional Description

FN8276 Rev.2.0

Page 18 of 30

Feb 25, 2021

5.

Functional Description

The HIP2103 has independent control inputs, LI and HI, for each output, LO and HO. There is no logic inversion

for these input/output pairs. To minimize the possibility of shoot-through failures of the bridge FETs caused by

improper LI and HI signals from an external controller, internal logic in the driver prevents both outputs being high

simultaneously. When either input is high, the high input must go low before a high on the other input propagates

to its respective drive output. If both inputs are high simultaneously, both outputs are low. If one input is high,

followed by the other input going high, the internal logic prevents any shoot through. Note that the internal logic

does not prevent shoot-through if the dead time provided by the external controller is not sufficiently long as

required by the turn-on and turn-off times of the bridge FETS.

If both inputs are high simultaneously for longer than 30µs, the driver initiates a Sleep Mode to reduce the bias

current to minimize the battery drain. When in Sleep Mode, the HO output is in a high-impedance state (2MΩ

between HO and HS) and the LO output is held low with an active 100Ω pull-down resistor. The 100Ω pull-down

prevents inadvertent shoot-through resulting from transients on the bridge voltage while both drivers are in Sleep

Mode.

The Undervoltage Lockout (UVLO) on VDD drives HO and LO low when VDD is less than the UV threshold. Sleep

Mode is initiated if UVLO is asserted for longer than 30µs.

The high-side driver bias is established by the boot capacitor connected between HB and HS. The charge on the

boot capacitor is provided by the internal boot FET that is connected between VDD and HB. The current path to

charge the boot capacitor is enabled (boot FET is on) when the drain voltage on the low-side bridge FET (VHO) is

<1V and HO = 0. When the boot FET is on, the boot capacitor is charged to approximately VDD.

The boot FET turns off when H0 = 1. The boot capacitor provides the charge necessary to turn on the FET and

maintains the bias voltage on the high-side driver for the duration of the period while the FET is on. See “Selecting

the Boot Capacitor Value” on page 19 for details on selecting the boot capacitor value.

The peak charge current is limited in amplitude by the inherent resistance of the boot FET and by the delta

voltage between VDD and the drain-source voltage of the low-side bridge FET (VHS) less the boot capacitor

voltage. Assuming that the low-side FET’s on-time is sufficiently long to fully charge the boot capacitor, the boot

voltage charges very close to VDD (less the voltage across the drain-source of the low-side bridge FET).

When the HI input transitions high, the high-side bridge FET is driven on. Because the HS node is connected to

the source of the high-side FET, the HS node rises almost to the level of the bridge voltage, VBAT (less the

conduction voltage across the bridge FET). Because the boot capacitor voltage is referenced to the source

voltage of the high-side FET, the HB node is VDD volts above the HS node. Simultaneously with HI = 1, the boot

FET is turned off preventing the boot capacitor from discharging back to VDD. Because the high-side driver circuit

is referenced to the HS node, the HO output is now approximately VHB + VBAT above ground.

During the low-to-high transition of the phase node (HS), the boot capacitor sources the necessary gate charge to

fully enhance the high-side bridge FET gate. After the gate of the bridge FET is fully charged, the boot capacitor

no longer sources charge to the gate but continues to provide bias current to the high-side driver through out the

period while the high-side bride FET is on.

To prevent the voltage on the boot capacitor from drooping excessively, the boot capacitor value must be sized

appropriately. If the boot voltage droops to the UVLO threshold, the high-side FET is turned off to prevent damage

due to insufficient gate voltage.

5.1

HIP2104 LDOs

The HIP2104 integrates two internal LDOs, VCC and VDD. The 3.3V on VCC provides bias for an external MCU

or other controller. The 12V on VDD provides bias for the gate driver outputs and bootstrap circuit on the HIP2104

and additionally for biasing the VDD pin on one or more HIP2103 when used in a 3-phase Brushless DC (BLDC)

or multi-phase DC/DC half-bridge topologies. The VCC LDO’s maximum output current is 75mA at 3.3V. The VDD

LDO’s maximum output is also 75mA at 12V. Note: Dynamic operating current on the HIP2103/HIP2104 drivers is

a function of operating frequency and capacitive loading, which determines the loading on the VDD LDO.