DSPIC33FJ12MC02ESS datasheet(98/284 Pages) MICROCHIP

98 / 284 page

dsPIC33FJ12MC201/202

DS70265B-page 96

Preliminary

OSCCON: OSCILLATOR CONTROL REGISTER

U-0

R-0

U-0

R/W-y

—COSC<2:0>

—NOSC<2:0>

bit 15

bit 8

R/W-0

R-0

U-0

R/C-0

U-0

R/W-0

CLKLOCK

IOLOCK

LOCK

—CF

—

LPOSCEN

OSWEN

bit 7

bit 0

Legend:

y = Value set from Configuration bits on POR

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

COSC<2:0>: Current Oscillator Selection bits (read-only)

000 = Fast RC oscillator (FRC)

001 = Fast RC oscillator (FRC) with PLL

010 = Primary oscillator (XT, HS, EC)

011 = Primary oscillator (XT, HS, EC) with PLL

100 = Secondary oscillator (SOSC)

101 = Low-Power RC oscillator (LPRC)

110 = Fast RC oscillator (FRC) with Divide-by-16

111 = Fast RC oscillator (FRC) with Divide-by-n

bit 11

Unimplemented: Read as ‘0’

bit 10-8

NOSC<2:0>: New Oscillator Selection bits

000 = Fast RC oscillator (FRC)

001 = Fast RC oscillator (FRC) with PLL

010 = Primary oscillator (XT, HS, EC)

011 = Primary oscillator (XT, HS, EC) with PLL

100 = Secondary oscillator (SOSC)

101 = Low-Power RC oscillator (LPRC)

110 = Fast RC oscillator (FRC) with Divide-by-16

111 = Fast RC oscillator (FRC) with Divide-by-n

bit 7

CLKLOCK: Clock Lock Enable bit

If clock switching is enabled and FSCM is disabled, (FOSC<FCKSM> = 0b01)

1 = Clock switching is disabled, system clock source is locked

0 = Clock switching is enabled, system clock source can be modified by clock switching

bit 6

IOLOCK: Peripheral Pin Select Lock bit

1 = Peripherial pin select is locked, write to peripheral pin select registers not allowed

0 = Peripherial pin select is not locked, write to peripheral pin select registers allowed

bit 5

LOCK: PLL Lock Status bit (read-only)

1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied

0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled

bit 4

Unimplemented: Read as ‘0’

bit 3

CF: Clock Fail Detect bit (read/clear by application)

1 = FSCM has detected clock failure

0 = FSCM has not detected clock failure

bit 2

Unimplemented: Read as ‘0’

DSPIC33FJ12MC02ESS Datasheet(PDF) 98 Page - Microchip Technology

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