STM32G47PBY6TR datasheet(228/229 Pages) STMICROELECTRONICS

228 / 229 page

Revision history

STM32G473xB STM32G473xC STM32G473xE

228/229

DS12712 Rev 3

30-Oct-2020

Updated:

– Table 1: Device summary

– Table 12: STM32G473xB/xC/xE pin definition

– Section 3.18: Analog-to-digital converter (ADC)

– Table 17: General operating conditions

– Table 21: Current consumption in Run and Low-power run modes, code with data

processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF)

– Table 22: Current consumption in Run and Low-power run modes, code with data

processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF)

– Table 23: Current consumption in Run and Low-power run modes, code with data

processing running from SRAM1

– Table 28: Current consumption in Sleep and Low-power sleep mode Flash ON

– Table 29: Current consumption in low-power sleep modes, Flash in power-down

– Table 30: Current consumption in Stop 1 mode

– Table 31: Current consumption in Stop 0 mode

– Table 32: Current consumption in Standby mode

– Table 51: ESD absolute maximum ratings

– Table 71: DAC 15MSPS characteristics

– Table 74: COMP characteristics

– Table 75: OPAMP characteristics

– Table 79: TIMx characteristics

– Table 84: SPI characteristics

– Table 85: I2S characteristics

– Table 104: QUADSPI characteristics in DDR mode

– Table 116: UFBGA121 - mechanical data

– Table 117: UFBGA121 - recommended PCB design rules

– Table 118: Package thermal characteristics

– Table 119: Ordering information

– Figure 76: UFBGA121 - outline

– Figure 77: UFBGA121 - recommended footprint

Added:

– Figure 74: LQFP128 - recommended footprint

– Table 13: STM32G473xB/xC/xE UFBGA121 pinout,

– Table 116: UFBGA121 - mechanical data

– Table 117: UFBGA121 - recommended PCB design rules

– Table 76: UFBGA121 - outline

– Table 77: UFBGA121 - recommended footprint

Table 120. Document revision history (continued)

Date

Revision

Changes

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