ST72325AR9-Auto datasheet(66/243 Pages) STMICROELECTRONICS

66 / 243 page

Obsolete

Product(s)

- Obsolete

Product(s)

Power saving modes

ST72325xxx-Auto

66/243

Doc ID 13770 Rev 3

Power saving modes

8.1

Introduction

To give a large measure of flexibility to the application in terms of power consumption, four

main power saving modes are implemented in the ST7 (see Figure 24): Slow, Wait (Slow

Wait), Active Halt and Halt.

After a RESET the normal operating mode is selected by default (Run mode). This mode

drives the device (CPU and embedded peripherals) by means of a master clock which is

based on the main oscillator frequency divided or multiplied by 2 (fOSC2).

From Run mode, the different power saving modes may be selected by setting the relevant

oscillator status.

Figure 24.

Power saving mode transitions

8.2

Slow mode

This mode has two targets:

●

To reduce power consumption by decreasing the internal clock in the device,

●

To adapt the internal clock frequency (fCPU) to the available supply voltage.

Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or

disables Slow mode and two CPx bits which select the internal slow frequency (fCPU).

In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU

and peripherals are clocked at this lower frequency (fCPU).

Note:

Slow Wait mode is activated when entering the Wait mode while the device is already in

Slow mode.

POWER CONSUMPTION

WAIT

SLOW

RUN

ACTIVE HALT

High

Low

SLOW WAIT

HALT

ST72325AR9-Auto Datasheet(PDF) 66 Page - STMicroelectronics

ST72325AR9-Auto Datasheet(HTML) 66 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL