TNETV2501INPGF datasheet(91/197 Pages) TI1

91 / 197 page

Functional Overview

December 2002 − Revised November 2008

SPRS206K

Table 3−30. Peripheral IDLE Status Register Bit Field Description (Continued)

BIT NAME

DESCRIPTION

RESET VALUE

ACCESS

BIT NO.

Reserved

SP1

McBSP1 bit

SP1 = 0:

McBSP1 is active

SP1 = 1:

McBSP1 is disabled

SP0

McBSP0 bit

SP0 = 0:

McBSP0 is active

SP0 = 1:

McBSP0 is disabled

TIM1

TIMER1 bit

TIM1 = 0:

TIMER1 is active

TIM1 = 1:

TIMER1 is disabled

TIM0

TIMER0 bit

TIM0 = 0:

TIMER0 is active

TIM0 = 1:

TIMER0 is disabled

3.10.7.5 Master IDLE Control Register (MICR)

Reserved

R, 00000000

Reserved

HPI

DMA

R, 000000

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3−30. Master IDLE Control Register Layout (0x9402)

Table 3−31. Master IDLE Control Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15−2

00000000000000

Reserved

HPI

R/W

HPI bit

HPI = 0:

HPI remains active when ISTR.MPIS becomes 1

HPI = 1:

HPI is disabled when ISTR.MPIS becomes 1

DMA

R/W

DMA bit

DMA = 0:

DMA remains active when ISTR.MPIS becomes 1

DMA = 1:

DMA is disabled when ISTR.MPIS becomes 1

TNETV2501INPGF Datasheet(PDF) 91 Page - Texas Instruments

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