TNETV2501INPGF datasheet(34/197 Pages) TI1

34 / 197 page

Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

Oscillator/Clock Pins

CLKOUT

O/Z

Clock output. CLKOUT can be set to reflect the clock of the Fast Peripherals Clock

Group, Slow Peripherals Clock Group, and the External Memory Interface Clock Group.

The CLKOUT pin is set to the internal clock SYSCLK1 during and after reset. SYSCLK1 is

set equal to a divided-by-four CLKIN or OSCOUT (depending on the state of the GPIO4

pin) during and after reset. SYSCLK1 is used to clock the Fast Peripheral Clock Group.

X2/CLKIN

Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as

the clock input.

Output pin from the internal oscillator for the crystal. If the internal oscillator is not

used, X1 should be left unconnected.

Multichannel Buffered Serial Port Pins

CLKR0

I/O/Z

C, F, G,

H, M

Receive clock input of McBSP0. The CLKR0 pin is configured as input after reset.

DR0

L, G

Serial data receive input of McBSP0

FSR0

I/O/Z

F, G, H,

Frame synchronization pulse for receive input of McBSP0. The FSR0 pin is

configured as input after reset.

CLKX0

I/O/Z

C, F, G,

H, M

Transmit clock of McBSP0. The CLKX0 pin is configured as input after reset.

DX0

O/Z

F, H, M

Serial data transmit output of McBSP0. The DX0 pin is in a high-impedance state

during and after reset.

FSX0

I/O/Z

F, G, H,

Frame synchronization pulse for transmit output of McBSP0. The FSX0 pin is

configured as input after reset.

CLKR1

I/O/Z

C, G,

H, M

Receive clock input of McBSP1. The CLKR1 pin is configured as input after reset.

DR1

L, G

Serial data receive input of McBSP1

FSR1

I/O/Z

F, G, H,

Frame synchronization pulse for receive input of McBSP1. The FSR1 pin is

configured as input after reset.

DX1

O/Z

F, H, M

Serial data transmit output of McBSP1. The DX1 pin is in a high-impedance state

during and after reset.

CLKX1

I/O/Z

C, F, G,

H, M

Transmit clock of McBSP1. The CLKX1 pin is configured as input after reset.

FSX1

I/O/Z

F, G, H,

Frame synchronization pulse for transmit output of McBSP1. The FSX1 pin is

configured as input after reset.

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

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