TNETV2501INPGF datasheet(69/197 Pages) TI1

69 / 197 page

Functional Overview

December 2002 − Revised November 2008

SPRS206K

3.9.5.3

PLL Divider 0 Register (PLLDIV0) (Prescaler)

This register controls the value of the PLL prescaler (Divider D0).

D0EN

Reserved

R/W, 1

R, 0000000

Reserved

PLLDIV0

R, 000

R/W, 00000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3−17. PLL Divider 0 Register Layout (0x1C8A)

Table 3−14. PLL Divider 0 Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

D0EN

R/W

Divider D0 enable

D0EN = 0:

Divider 0 disabled

D0EN = 1:

Divider 0 enabled

Reserved

14:5

0000000000

Reserved. Reads return 0. Writes have no effect.

PLLDIV0

4:0

R/W

00000

Divider D0 ratio

PLLDIV0 = 00000:

Divide by 1

PLLDIV0 = 00001:

Divide by 2

PLLDIV0 = 00010:

Divide by 3

PLLDIV0 = 00011:

Divide by 4

PLLDIV0 = 00100:

Divide by 5

PLLDIV0 = 00101:

Divide by 6

PLLDIV0 = 00110:

Divide by 7

PLLDIV0 = 00111:

Divide by 8

PLLDIV0 = 01000:

Divide by 9

PLLDIV0 = 01001:

Divide by 10

PLLDIV0 = 01010:

Divide by 11

PLLDIV0 = 01011:

Divide by 12

PLLDIV0 = 01100:

Divide by 13

PLLDIV0 = 01101:

Divide by 14

PLLDIV0 = 01110:

Divide by 15

PLLDIV0 = 01111:

Divide by 16

PLLDIV0 = 10000:

Divide by 17

PLLDIV0 = 10001:

Divide by 18

PLLDIV0 = 10010:

Divide by 19

PLLDIV0 = 10011:

Divide by 20

PLLDIV0 = 10100:

Divide by 21

PLLDIV0 = 10101:

Divide by 22

PLLDIV0 = 10110:

Divide by 23

PLLDIV0 = 10111:

Divide by 24

PLLDIV0 = 11000:

Divide by 25

PLLDIV0 = 11001:

Divide by 26

PLLDIV0 = 11010:

Divide by 27

PLLDIV0 = 11011:

Divide by 28

PLLDIV0 = 11100:

Divide by 29

PLLDIV0 = 11101:

Divide by 30

PLLDIV0 = 11110:

Divide by 31

PLLDIV0 = 11111:

Divide by 32

TNETV2501INPGF Datasheet(PDF) 69 Page - Texas Instruments

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