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TNETV6446AINZWT Datasheet(PDF) 137 Page - Texas Instruments |
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TNETV6446AINZWT Datasheet(HTML) 137 Page - Texas Instruments |
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137 / 227 page  EM_CS[5:2] 25 Asserted Deasserted 2 2 EM_BA[1:0] EM_A[21:0] EM_D[15:0] EM_WE EM_WAIT SETUP STROBE Extended Due to EM_WAIT STROBE HOLD 28 TMS320DM6446 www.ti.com SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 Figure 6-24. EM_WAIT Write Timing Requirements 6.10.2 DDR2 Memory Controller The DDR2 Memory Controller is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM Devices and can interface to either 16-bit or 32-bit DDR2 SDRAM devices. For details on the DDR2 Memory Controller, see the TMS320DM644x DMSoC Peripherals Overview Reference Guide (literature number SPRUE19) and the TMS320DM644x DMSoC DDR2 Memory Controller User's Guide (literature number SPRUE22). DDR2 SDRAM plays a key role in a DaVinci-based system. Such a system is expected to require a significant amount of high-speed external memory for: • Buffering of input image data from sensors or video sources • Intermediate buffering for processing/resizing of image data in the VPFE • Numerous OSD display buffers • Intermediate buffering for large raw Bayer data image files while performing image processing functions • Buffering for intermediate data while performing video encode and decode functions • Storage of executable code for both the ARM and DSP A memory map of the DDR2 Memory Controller registers is shown in Table 6-36. Table 6-36. DDR2 Memory Controller Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C4 004C DDRVTPER DDR2 VTP Enable Register 0x01C4 2030 DDRVTPR DDR2 VTP Register 0x2000 0000 - 0x2000 0003 - Reserved 0x2000 0004 SDRSTAT SDRAM Status Register 0x2000 0008 SDBCR SDRAM Bank Configuration Register 0x2000 000C SDRCR SDRAM Refresh Control Register 0x2000 0010 SDTIMR SDRAM Timing Register 0x2000 0014 SDTIMR2 SDRAM Timing Register 2 0x2000 0020 PBBPR Peripheral Bus Burst Priority Register 0x2000 0024 - 0x2000 00BF - Reserved 0x2000 00C0 IRR Interrupt Raw Register 0x2000 00C4 IMR Interrupt Masked Register 0x2000 00C8 IMSR Interrupt Mask Set Register Copyright © 2005–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 137 Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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