TNETV6446AINZWT datasheet(138/227 Pages) TI1

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DDR_CLK0

TMS320DM6446

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

www.ti.com

Table 6-36. DDR2 Memory Controller Registers (continued)

HEX ADDRESS RANGE

ACRONYM

0x2000 00CC

IMCR

Interrupt Mask Clear Register

0x2000 00D0 - 0x2000 00E3

Reserved

0x2000 00E4

DDRPHYCR

DDR PHY Control Register

0x2000 00E8 - 0x2000 00EF

Reserved

0x2000 00F0

VTPIOCR

VTP IO Control Register

0x2000 00F4 - 0x2000 7FFF

Reserved

6.10.2.1 DDR2 Memory Controller Electrical Data/Timing

The Implementing DDR2 PCB Layout on the TMS320DM644x DSP application report (literature number

SPRAAC5) specifies a complete DDR2 interface solution for the DM6446 as well as a list of compatible

DDR2 devices. TI has performed the simulation and system characterization to ensure all DDR2 interface

timings in this solution are met.

TI only supports board designs that follow the guidelines outlined in the Implementing DDR2 PCB Layout

on the TMS320DM644x DSP application report (literature number SPRAAC5).

Table 6-37. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory

Controller(1) (2)(see Figure 6-25)

A-513,

-810

-594

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

tc(DDR_CLK0)

Cycle time, DDR_CLK0

5.29

f(DDR_CLK0)

Frequency, DDR_CLK0

125

189

125

167

MHz

(1)

DDR_CLK0 cycle time = 2 x PLL2 - SYSCLK2 cycle time.

(2)

The PLL2 Controller must be programmed such that the resulting DDR_CLK0 clock frequency is within the specified range.

Figure 6-25. DDR2 Memory Controller Clock Timing

138

Peripheral and Electrical Specifications

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