TNETV6446AINZWT datasheet(62/227 Pages) TI1

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TMS320DM6446

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

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3.2

Power Considerations

Global device power domains are controlled by the Power and Sleep Controller, except as shown in the

following sections.

3.2.1

Power Configurations at Reset

As described in Section 6.3.1.3, DM6446 Power and Clock Domains, the DM6446 has two power

domains: Always On and DSP. There is a shorting switch between the two power domains that must be

opened when the DSP domain is powered off and closed when the DSP domain is powered on.

The CHP_SHRTSW register, shown in Figure 3-1, controls the shorting switch between the device

always-on and DSP power domains. This switch should be enabled after powering-up the DSP domain.

Setting the DSPPWRON bit to '1’ closes (enables) the switch and enables the DSP power domain. The

default switch value is determined by the DSP_BT configuration input. If DSP self boot is selected

(DSP_BT=1), the DSP will be powered-up and DSPPWRON will be set to a value of '1'. For ARM boot

operation (DSP_BT=0), DSPPWRON will be set to the disable value of '0' and must be set by the ARM

before the DSP domain power is turned on.

Note: Once the DSP power domain is enabled (powered up), it cannot be disabled (powered down).

Dynamic power down of the DSP is not supported on this device.

Figure 3-1. CHP_SHRTSW Register

RESERVED

DSPPWRON

R-0000 0000 0000 0000 0000 0000 0000 000

R/W-L

LEGEND: R = Read, W = Write, n = value at reset, L = pin state latched at reset rising

Table 3-2. CHP_SHRTSW Register Description

NAME

DESCRIPTION

DSPPWRON

DSP power domain enable.

0 = Shorting switch open

1 = Shorting switch closed

3.2.2

Power Configurations after Reset

The VDD3P3V_PWDN register controls power to the 3.3V I/O buffers for MMC/SD/SDIO and GPIOV33.

The 3.3V I/Os are separated into two groups for independent control as shown in Figure 3-2 and

described in Table 3-3. By default, these pins are all disabled at reset.

Figure 3-2. VDD3P3V_PWDN Register

RESERVED

IOPWDN1

IOPWDN0

R-0000 0000 0000 0000 0000 0000 0000 00

R/W-1

LEGEND: R = Read, W = Write, n = value at reset

Table 3-3. VDD3P3V_PWDN Register Description

NAME

DESCRIPTION

IOPWDN0

GIOV33 I/O Powerdown controls GIOV33[16:0] pins.

0 = I/O buffers powered up

1 = I/O buffers powered down

IOPWDN1

MMC/SD/SDIO I/O Powerdown controls SD_CLK, SD_CMD, SD_DATA[3:0] pins.

0 = I/O buffers powered up

1 = I/O buffers powered down

Device Configurations

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