TNETV6446AINZWT datasheet(133/227 Pages) TI1

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TMS320DM6446

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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

6.10.1.2

EMIFA Electrical Data/Timing

Table 6-34. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module(1)

(see Figure 6-21 and Figure 6-22)

A-513,

-594,

NO.

UNIT

-810

MIN

MAX

READS and WRITES

tw(EM_WAIT)

Pulse duration, EM_WAIT assertion and deassertion

READS

tsu(EMDV-EMOEH)

Setup time, EM_D[15:0] valid before EM_OE high

10.5

th(EMOEH-EMDIV)

Hold time, EM_D[15:0] valid after EM_OE high

tsu (EMWAIT-EMOEH)

Setup time, EM_WAIT asserted before EM_OE high(2)

4E + 10.4

WRITES

t su(EMWAIT-EMWEH)

Setup time, EM_WAIT asserted before EM_WE high(2)

4E + 10.4

(1)

E = SYSCLK5 period in ns for EMIFA. For example, when running the DSP CPU at 594 MHz, use E = 10.1 ns. For example, when

running the DSP CPU at 810 MHz, use E = 7.4 ns.

(2)

Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended

wait states. Figure 6-23 and Figure 6-24 describe EMIF transactions that include extended wait states inserted during the STROBE

phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where

the HOLD phase would begin if there were no extended wait cycles.

Peripheral and Electrical Specifications

133

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