TNETV1644ZDU6 datasheet(117/306 Pages) TI1

117 / 306 page

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, PCI pins span across the

following Pin Mux Blocks: Host Block, EMIFA/VPSS Block Sub-Block 0 and Sub-Block 3, PCI Data Block,

and GPIO Block. For proper PCI operation, PCI must be selected in all of these Pin Mux Blocks.

Table 3-23 provides a different view of the Host Block pin muxing, showing the Host Block function based

on PINMUX1 settings. The selection options are also shown pictorially in Figure 3-11.

If EMAC operation is desired, EMAC must be placed in reset before programming PINMUX1.HOSTBK to

select EMAC pins.

Table 3-23. Host Block Function Selection

PINMUX1 SETTING

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

PCIEN(1)

HOSTBK

PCI: PCICLK, PCBE2, PCBE1, PCBE0, PFRAME, PIDRDY, PTRDY,

PCI

000

PDEVSEL, PSTOP, PPER, PSERR, PPAR, AD[18:05], AD[03]

(Default if PCIEN = 1)

Internal pullup/pulldown on all these pins are disabled.

001 to 111

Reserved

GPIO (27)

000

GPIO: GP[83:57]

(Default if PCIEN = 0)

HPI: HHWIL, HCNTL[1:0], HR/W, HDS2, HDS1, HRDY, HCS, HINT, HAS,

001

HPI + GPIO (1)

HD[15:0]

GPIO: GP[57]

VLYNQ: VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0],

VLYNQ_TXD[3:0]

010

VLYNQ + GPIO (17)

GPIO: GP[83:67]

VLYNQ: VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0],

VLYNQ_TXD[3:0]

EMAC (MII): TXCLK, CRS, COL, TXD[3:0], RXDV, TXEN, RXER, RXCLK,

011

VLYNQ + EMAC (MII) + MDIO

RXD[3:0]

MDIO: MDC, MDIO

If EMAC operation is desired, EMAC must be placed in reset before

programming PINMUX1.HOSTBK to select EMAC pins.

EMAC (MII): TXCLK, CRS, COL, TXD[3:0], RXDV, TXEN, RXER, RXCLK,

RXD[3:0]

MDIO: MDC, MDIO

100

EMAC (MII) + MDIO + GPIO (10)

GPIO: GP[66:57]

If EMAC operation is desired, EMAC must be placed in reset before

programming PINMUX1.HOSTBK to select EMAC pins.

101 to 111

Reserved

(1)

If PCIEN = 1, the internal pullup/pulldown on all Host Block pins are disabled. If PCIEN = 0, the internal pullup/pulldown on all Host

Block pins are enabled.

The PINMUX1.PCIEN field is read-only, and its setting is determined by the PCIEN configuration pin.

Based on the PCIEN configuration pin setting, the 27 pins in the Host Block defaults to either PCI or GPIO

function.

In addition, the VDD3P3V_PWDN.HOST field determines the power state of the Host Block pins. The

Host Block pins default to powered up. For more details on the VDD3P3V_PWDN.HOST field, see

Section 3.2, Power Considerations.

Submit Documentation Feedback

Device Configurations

117

TNETV1644ZDU6 Datasheet(PDF) 117 Page - Texas Instruments

TNETV1644ZDU6 Datasheet(HTML) 117 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL