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TNETV1644ZDU6 Datasheet(PDF) 113 Page - Texas Instruments |
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TNETV1644ZDU6 Datasheet(HTML) 113 Page - Texas Instruments |
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113 / 306 page  TMS320DM6437 Digital Media Processor www.ti.com SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 Table 3-21. Multiplexed Pins on DM6437 (continued) SIGNAL PINMUX DESCRIPTION ZWT ZDU NAME PINMUX GROUP CONTROLLED BY PINMUX BIT FIELDS NO. NO. VLYNQ_CLOCK/PCICLK/GP[57] A7 A8 Host Block PCIEN, HOSTBK HD0/VLYNQ_SCRUN/AD18/GP[58] C8 B9 Host Block PCIEN, HOSTBK HD1/VLYNQ_RXD0/AD16/GP[59] D7 C9 Host Block PCIEN, HOSTBK HD2/VLYNQ_RXD1/AD17/GP[60] A8 A9 Host Block PCIEN, HOSTBK HD3/VLYNQ_RXD2/PCBE2/GP[61] B7 B8 Host Block PCIEN, HOSTBK HD4/VLYNQ_RXD3/PFRAME/GP[62] C7 C8 Host Block PCIEN, HOSTBK HD5/VLYNQ_TXD0/PIRDY/GP[63] A6 A7 Host Block PCIEN, HOSTBK HD6/VLYNQ_TXD1/PTRDY/GP[64] D6 C7 Host Block PCIEN, HOSTBK HD7/VLYNQ_TXD2/PDEVSEL/GP[65] B6 B7 Host Block PCIEN, HOSTBK HD8/VLYNQ_TXD3/PPERR/GP[66] A5 A6 Host Block PCIEN, HOSTBK HD9/MCOL/PSTOP/GP[67] C6 C6 Host Block PCIEN, HOSTBK HD10/MCRS/PSERR/GP[68] B5 B6 Host Block PCIEN, HOSTBK HD11/MTXD3/PCBE1/GP[69] C5 A5 Host Block PCIEN, HOSTBK HD12/MTXD2/PPAR/GP[70] D5 C5 Host Block PCIEN, HOSTBK HD13/MTXD1/AD14/GP[71] B4 B4 Host Block PCIEN, HOSTBK HD14/MTXD0/AD15/GP[72] D4 B5 Host Block PCIEN, HOSTBK HD15/MTXCLK/AD12/GP[73] A4 A4 Host Block PCIEN, HOSTBK HHWIL/MRXDV/AD13/GP[74] C4 D3 Host Block PCIEN, HOSTBK HCNTL1/MTXEN/AD11/GP[75] D3 C4 Host Block PCIEN, HOSTBK HCNTL0/MRXER/AD10/GP[76] B3 B2 Host Block PCIEN, HOSTBK HR/W/MRXCLK/AD8/GP[77] A3 A3 Host Block PCIEN, HOSTBK HDS2/MRXD0/AD9/GP[78] C3 C2 Host Block PCIEN, HOSTBK HDS1/MRXD1/AD7/GP[79] B2 B3 Host Block PCIEN, HOSTBK HRDY/MRXD2/PCBE0/GP[80] D2 C3 Host Block PCIEN, HOSTBK HCS/MDCLK/AD5/GP[81] C1 D1 Host Block PCIEN, HOSTBK HINT/MRXD3/AD6/GP[82] C2 D2 Host Block PCIEN, HOSTBK HAS/MDIO/AD3/GP[83] D1 C1 Host Block PCIEN, HOSTBK AD0/GP[0] E1 E1 GPIO Block PCIEN AD1/GP[1] E2 E2 GPIO Block PCIEN AD2/GP[2] E3 F1 GPIO Block PCIEN AD4/GP[3] E4 F2 GPIO Block PCIEN GP[4]/PWM1 F3 F3 PWM1Block PWM1BK ACLKR0/CLKX0/GP[99] H1 J1 Serial Port Sub-Block 0 SPBK0 AFSR0/DR0/GP[100] H4 K3 Serial Port Sub-Block 0 SPBK0 AHCLKR0/CLKR0/GP[101] J2 K1 Serial Port Sub-Block 0 SPBK0 AXR0[3]/FSR0/GP[102] G4 J3 Serial Port Sub-Block 0 SPBK0 AXR0[2]/FSX0/GP[103] H3 J2 Serial Port Sub-Block 0 SPBK0 AXR0[1]/DX0/GP[104] J3 K2 Serial Port Sub-Block 0 SPBK0 AXR0[0]/FSR1/GP[105] H2 H2 Serial Port Sub-Block 1 SPBK1 ACLKX0/CLKX1/GP[106] F1 G1 Serial Port Sub-Block 1 SPBK1 AFSX0/DX1/GP[107] G2 G2 Serial Port Sub-Block 1 SPBK1 AHCLKX0/CLKR1/GP[108] G1 H1 Serial Port Sub-Block 1 SPBK1 AMUTEIN0/FSX1/GP[109] F2 G3 Serial Port Sub-Block 1 SPBK1 AMUTE0/DR1/GP[110] G3 H3 Serial Port Sub-Block 1 SPBK1 HECC_RX/TINP1L/URXD1/GP[56] L4 P3 Timer 1 Block TIM1BK Submit Documentation Feedback Device Configurations 113 |
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