PM0214 datasheet(215/245 Pages) STMICROELECTRONICS

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PM0214

Core peripherals

244

4.4.7

Configuration and control register (CCR)

Address offset: 0x14

Reset value: 0x0000 0200

Required privilege: Privileged

The CCR controls entry to Thread mode and enables:

•

The handlers for NMI, hard fault and faults escalated by FAULTMASK to ignore bus

faults

•

Trapping of divide by zero and unaligned accesses

•

Access to the STIR by unprivileged software, see Software trigger interrupt register

(NVIC_STIR) on page 201.

3029

Reserved

STK

ALIGN

BFHF

NMIGN

Reserved

DIV_0_

TRP

ALIGN_

TRP

Res.

USER

SET

MPEND

NON

BASE

THRD

ENA

Bits 31:10

Reserved, must be kept cleared

Bit 9

STKALIGN

Configures stack alignment on exception entry. On exception entry, the processor uses bit 9 of

the stacked PSR to indicate the stack alignment. On return from the exception it uses this

stacked bit to restore the correct stack alignment.

0: 4-byte aligned

1: 8-byte aligned

Bit 8

BFHFNMIGN

Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store

instructions. This applies to the hard fault, NMI, and FAULTMASK escalated handlers. Set this

bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of

this bit is to probe system devices and bridges to detect control path problems and fix them.

0: Data bus faults caused by load and store instructions cause a lock-up

1: Handlers running at priority -1 and -2 ignore data bus faults caused by load and store

instructions.

Bits 7:5

Reserved, must be kept cleared

Bit 4

DIV_0_TRP

Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a

divisor of 0:

0: Do not trap divide by 0

1: Trap divide by 0.

When this bit is set to 0, a divide by zero returns a quotient of 0.

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