PM0214 datasheet(71/245 Pages) STMICROELECTRONICS

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PM0214

The STM32 Cortex-M4 instruction set

244

Table 26 shows the range of offsets for immediate, pre-indexed and post-indexed forms.

Restrictions

•

For load instructions

–

Rt can be SP or PC for word loads only

–

Rt must be different from Rt2 for two-word loads

–

Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms

•

When Rt is PC in a word load instruction

–

bit[0] of the loaded value must be 1 for correct execution

–

A branch occurs to the address created by changing bit[0] of the loaded value to 0

–

If the instruction is conditional, it must be the last instruction in the IT block

•

For store instructions

–

Rt can be SP for word stores only

–

Rt must not be PC

–

Rn must not be PC

–

Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms

Condition flags

These instructions do not change the flags.

Examples

LDR R8, [R10]

; loads R8 from the address in R10.

LDRNE R2, [R5, #960]!; loads (conditionally) R2 from a word

; 960 bytes above the address in R5, and

; increments R5 by 960.

STR R2, [R9,#const-struc]; const-struc is an expression evaluating

; to a constant in the range 0-4095.

STRH R3, [R4], #4; Store R3 as halfword data into address in

; R4, then increment R4 by 4

LDRD R8, R9, [R3, #0x20]; Load R8 from a word 32 bytes above the

; address in R3, and load R9 from a word 36

; bytes above the address in R3

STRD R0, R1, [R8], #-16; Store R0 to address in R8, and store R1 to

; a word 4 bytes above the address in R8,

; and then decrement R8 by 16.

Table 26. Immediate, pre-indexed and post-indexed offset ranges

Instruction type

Immediate offset

Pre-indexed

Post-indexed

Word, halfword, signed

halfword, byte, or signed byte

-255 to 4095

-255 to 255

Two words

Multiple of 4 in the

range -1020 to 1020

Multiple of 4 in the

range -1020 to 1020

Multiple of 4 in the

range -1020 to 1020

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