PM0214 datasheet(77/245 Pages) STMICROELECTRONICS

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PM0214

The STM32 Cortex-M4 instruction set

244

3.4.7

PUSH and POP

Push registers onto, and pop registers off a full-descending stack. PUSH and POP are

synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the access

based on SP, and with the final address for the access written back to the SP. PUSH and

POP are the preferred mnemonics in these cases.

Syntax

PUSH{cond} reglist

POP{cond} reglist

where:

•

‘cond’ is an optional condition code (see Conditional execution on page 64)

•

‘reglist’ is a non-empty list of registers (or register ranges), enclosed in braces.

Commas must separate register lists or ranges (see Examples on page 76).

Operation

•

PUSH stores registers on the stack in order of decreasing register numbers, with the

highest numbered register using the highest memory address and the lowest

numbered register using the lowest memory address.

•

POP loads registers from the stack in order of increasing register numbers, with the

lowest numbered register using the lowest memory address and the highest numbered

•

PUSH uses the value in the SP register minus four as the highest memory address,

POP uses the SP register value as the lowest memory address, implementing a full-

descending stack. On completion, PUSH updates the SP register to point to the

location of the lowest store value, POP updates the SP register to point to the location

above the highest location loaded.

•

If a POP instruction includes PC in its reglist, a branch to this location is performed

when the POP instruction has completed. Bit[0] of the value read for the PC is used to

update the APSR T-bit. This bit must be 1 to ensure correct operation. See LDM and

STM on page 75 for more information.

Restrictions

In these instructions:

•

‘reglist’ must not contain SP

•

For the PUSH instruction, reglist must not contain PC

•

For the POP instruction, reglist must not contain PC if it contains LR.

When PC is in reglist in a POP instruction: bit[0] of the value loaded to the PC must be 1

for correct execution, and a branch occurs to this halfword-aligned address. If the

instruction is conditional, it must be the last instruction in the IT block.

Condition flags

These instructions do not change the flags.

Examples

PUSH {R0,R4-R7} ; Push R0,R4,R5,R6,R7 onto the stack

PUSH {R2,LR}

; Push R2 and the link-register onto the stack

POP

{R0,R6,PC} ; Pop r0,r6 and PC from the stack, then branch to new PC.

PM0214 Datasheet(PDF) 77 Page - STMicroelectronics

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