PCF8811USLASH2DASLASH1 datasheet(33/81 Pages) NXP

33 / 81 page

PCF8811_4

Product data sheet

Rev. 04 — 27 June 2008

33 of 81

NXP Semiconductors

PCF8811

80 x 128 pixels matrix LCD driver

of the acknowledge-related clock pulse (set-up and hold times must be taken into

consideration). A master receiver must signal an end-of-data to the transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In this

event the transmitter must leave the data line HIGH to enable the master to generate a

STOP condition.

11.2 I2C-bus Hs-mode protocol

The PCF8811 is a slave receiver/transmitter. If data is to be read from the device, the

SDAH pad must be connected, otherwise the SDAH pad is unused.

Hs-mode can only commence after the following conditions:

• START condition (S)

• 8-bit master code (0000 1xxx)

• Not-acknowledge bit (A)

The master code has two functions: it allows arbitration and synchronization between

competing masters at F/S-mode speeds, resulting in one winner. The master code also

indicates the beginning of an Hs-mode transfer. These conditions are shown in Figure 29

and Figure 30.

Fig 28. Acknowledge on the I2C-bus

mbc602

START

condition

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

Fig 29. Data transfer format in Hs-mode

F/S-mode

Hs-mode (current-source for SCLH enabled)

F/S-mode

msc616

A/A

DATA

(n bytes + ack.)

R/W

MASTER CODE

SLAVE ADD.

Hs-mode continues

Sr SLAVE ADD.

PCF8811U/2DA/1 Datasheet(PDF) 33 Page - NXP Semiconductors

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