PCF8811USLASH2DASLASH1 datasheet(19/81 Pages) NXP

19 / 81 page

PCF8811_4

Product data sheet

Rev. 04 — 27 June 2008

19 of 81

NXP Semiconductors

PCF8811

80 x 128 pixels matrix LCD driver

7.2.5 Display address counter

The display is generated by reading out the RAM content for 2, 4 or 8 rows

simultaneously, depending on the current selected display size. This content is processed

with the corresponding set of 2, 4 or 8 orthogonal functions and so generates the signals

for switching the pixels in the display on or off according to the RAM content. The value p

deﬁnes the number of rows which are simultaneously selected. It is possible to set the p

value for the display sizes 64 and 80 manually to p = 4; see Table 10.

The display status (all dots on/off and normal/inverse video) is set by the bits DON, DAL

and E in the command display control; see Table 11.

7.2.6 LCD row and column drivers

The PCF8811 contains 80 row and 128 column drivers, which connect the appropriate

LCD bias voltages in sequence to the display in accordance with the data to be displayed.

Addressing

Data is written in bytes to the RAM matrix of the PCF8811 as shown in Figure 5. The

display RAM has a matrix of 80

× 128 bits. The columns are addressed by the address

pointer. The address ranges are: X = 0 to 127 (111 1111), Y = 0 to 9 (1001). The Y

address represents the bank number. The effective X and Y addresses are programmed

in such an order to use the PCF8811 with different display sizes, without additional

loading of the microprocessor. Addresses outside these ranges are not allowed. The icon

row when enabled is always row 79 and therefore located in bank 9.

PCF8811U/2DA/1 Datasheet(PDF) 19 Page - NXP Semiconductors