PCF8811USLASH2DASLASH1 datasheet(29/81 Pages) NXP

29 / 81 page

PCF8811_4

Product data sheet

Rev. 04 — 27 June 2008

29 of 81

NXP Semiconductors

PCF8811

80 x 128 pixels matrix LCD driver

Any instruction can be sent in any order to the PCF8811; the MSB is transmitted ﬁrst. The

serial interface is initialized when SCE is HIGH. In this state, SCLK clock pulses have no

effect and no power is consumed by the serial interface. A falling edge on SCE enables

the serial interface and indicates the start of data transmission.

Figure 21, Figure 22 and Figure 23 show the protocol of the write mode:

• when SCE is HIGH, SCLK clocks are ignored; during the HIGH time of SCE the serial

interface is initialized

• SCLK must be LOW on the falling SCE edge; see Figure 41

• SDATA is sampled on the rising edge of SCLK

• D/C indicates, whether the byte is a command (D/C = 0) or RAM data (D/C = 1); it is

sampled on the ﬁrst rising SCLK edge

• If SCE stays LOW after the last bit of a data/command byte, the serial interface

receives the D/C bit of the next byte on the next rising edge of SCLK; see Figure 22

• A reset pulse RES interrupts the transmission. The data being written into the RAM

may be corrupted. The registers are cleared. If SCE is LOW after the rising edge of

RES, the serial interface is ready to receive the D/C bit of a data/command byte;

see Figure 23.

Fig 20. Serial data stream; write mode

D/C DB7 DB6 DB5 DB4 DB3

Transmission Byte (TB) (command byte or data byte)

DB2 DB1 DB0

MSB

LSB

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D/C

Fig 21. Write mode: a control bit followed by a transmission byte

SCE

SCLK

SDATA

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

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PCF8811U/2DA/1 Datasheet(PDF) 29 Page - NXP Semiconductors

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