LTC2420 datasheet(20/36 Pages) LINER

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LTC2420

Internal Serial Clock, 2-Wire I/O,

Continuous Conversion

This timing mode uses a 2-wire, all output (SCK and SDO)

interface. The conversion result is shifted out of the device

by an internally generated serial clock (SCK) signal, see

Figure 11. CS may be permanently tied to ground (Pin 4),

simplifying the user interface or isolation barrier.

The internal serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately 0.5ms after VCC exceeds 2.2V. An internal

weak pull-up is active during the POR cycle; therefore, the

internal serial clock timing mode is automatically selected

if SCK is not externally driven LOW (if SCK is loaded such

that the internal pull-up cannot pull the pin HIGH, the

external SCK mode will be selected).

During the conversion, the SCK and the serial data output

pin (SDO) are HIGH (EOC = 1). Once the conversion is

complete, SCK and SDO go LOW (EOC = 0) indicating the

conversion has finished and the device has entered the

low power sleep state. The part remains in the sleep state

a minimum amount of time (1/2 the internal SCK period)

APPLICATIO S I FOR ATIO

then immediately begins outputting data. The data output

cycle begins on the first rising edge of SCK and ends after

the 24th rising edge. Data is shifted out the SDO pin on

each falling edge of SCK. The internally generated serial

clock is output to the SCK pin. This signal may be used

to shift the conversion result into external circuitry. EOC

can be latched on the first rising edge of SCK and the last

bit of the conversion result can be latched on the 24th

rising edge of SCK. After the 24th rising edge, SDO goes

HIGH (EOC = 1) indicating a new conversion is in progress.

SCK remains HIGH during the conversion.

Internal Serial Clock, Autostart Conversion

This timing mode is identical to the internal serial clock,

2-wire I/O described above with one additional feature.

Instead of grounding CS, an external timing capacitor is

tied to CS.

While the conversion is in progress, the CS pin is held

HIGH by an internal weak pull-up. Once the conversion is

complete, the device enters the low power sleep state and

an internal 25nA current source begins discharging the

SDO

SCK

(INTERNAL)

LSB20

MSB

EXR

SIG

BIT 4

BIT 0

BIT 19

BIT 18

BIT 20

BIT 21

BIT 22

EOC

BIT 23

SLEEP

DATA OUTPUT

CONVERSION

2420 F11

VCC

VREF

SCK

VIN

SDO

GND

VREF

0.1V TO VCC

VIN

–0.12VREF TO 1.12VREF

µF

2.7V TO 5.5V

LTC2420

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

VCC

Figure 11. Internal Serial Clock, Continuous Operation

LTC2420 Datasheet(PDF) 20 Page - Linear Technology

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